Dear Champs,
I am asking this for our customers.
We have some questions about the computational power analysis when only two-phase interleaved boost PFC is used without the valley switching.
In the doc, it says "With the nested CLA option, the CPU burden can be significantly reduced since the PWM ISR occupies close to 40% of the CPU usage.".
1) Does that mean that we can assume it takes about 40 MIPS on C28X if only two-phase interleaved boost PFC is used?
2) If yes, this 40 MIPS means a) or b) or else?
a) 200 KHz-PWM switching, 100 KHz-current loop ISR (fast control ISR) for one total current measurement, one-compensator computation?
b) 200 KHz-PWM switching, 100 KHz-current loop ISR (fast control ISR) for two-phase current measurement separately, two-compensator computation (that is, two duty commands for each phase)?
3) In this case, do you use the TMU hardware accelerator for the feed-forward algorithm like division, trigonometric operations, root-mean-square. Or do you use look-up-table based methods for those operations?
Thank you in advance.
Wayne Huang
