Tool/software: Code Composer Studio
Hi,
I have tried to toggle a GPIO14 of F2808 µC using a delay routine. I have set to operate the device at 100MHz. The clock is sourced by an external 20MHz crystal oscillator and using the internal PLL settings, it is overclocked to 100MHz. But when I test the delay routine, it takes only 1550000 controller cycles for 1 second to elapse. Can someone tell me if I have set the FCPU and clock settings correctly?
GPIO14 Toggle code:
/*
* main_LED.c
*
* Created on: 14.10.2019
* Author: Frederic Leo
*/
#include "DSP280x_Device.h" // DSP280x Header file Include File
#include "DSP280x_GlobalPrototypes.h"
#include "DSP280x_Examples.h" // DSP280x Examples Include File
void delay_loop(void);
void main()
{
// WARNING: Always ensure you call memcpy before running any functions from RAM
// InitSysCtrl includes a call to a RAM based function and without a call to
// memcpy first, the processor will go "into the weeds"
#ifdef _FLASH
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the f2802x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initialize GPIO:
// This example function is found in the f2802x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the f2802x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in f2802x_DefaultIsr.c.
// This function is found in f2802x_PieVect.c.
InitPieVectTable();
// Disable Protection
EALLOW; // This is needed to write to EALLOW protected registers
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0; // Set as GPIO
GpioCtrlRegs.GPADIR.bit.GPIO14 = 1; // GPIO14 is output
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14
EDIS; // This is needed to disable write to EALLOW protected registers
for(;;)
{
GpioDataRegs.GPATOGGLE.bit.GPIO14 = 1; // Toggle GPIO14
//1s delay
delay_loop();
}
}
void delay_loop(void)
{
long i;
for (i = 0; i < 1550000; i++) {}
}
My PLL settings:
// TI File $Revision: /main/8 $
// Checkin $Date: April 4, 2007 17:18:30 $
//###########################################################################
//
// FILE: DSP280x_Examples.h
//
// TITLE: DSP280x Device Definitions.
//
//###########################################################################
// $TI Release: DSP280x Header Files V1.50 $
// $Release Date: September 10, 2007 $
//###########################################################################
#ifndef DSP280X_EXAMPLES_H
#define DSP280X_EXAMPLES_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------
Specify the PLL control register (PLLCR) and clock in divide (CLKINDIV) value.
if CLKINDIV = 0: SYSCLKOUT = (OSCCLK * PLLCR)/2
if CLKINDIV = 1: SYSCLKOUT = (OSCCLK * PLLCR)
-----------------------------------------------------------------------------*/
#define DSP28_CLKINDIV 0 // Enable /2 for SYSCLKOUT
//#define DSP28_CLKINDIV 1 // Disable /2 for SYSCKOUT
#define DSP28_PLLCR 10
//#define DSP28_PLLCR 9
//#define DSP28_PLLCR 8
//#define DSP28_PLLCR 7
//#define DSP28_PLLCR 6 // Uncomment for 60 MHz devices [60 MHz = (20MHz * 6)/2]
//#define DSP28_PLLCR 5
//#define DSP28_PLLCR 4
//#define DSP28_PLLCR 3
//define DSP28_PLLCR 2
//#define DSP28_PLLCR 1
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
//----------------------------------------------------------------------------
/*-----------------------------------------------------------------------------
Specify the clock rate of the CPU (SYSCLKOUT) in nS.
Take into account the input clock frequency and the PLL multiplier
selected in step 1.
Use one of the values provided, or define your own.
The trailing L is required tells the compiler to treat
the number as a 64-bit value.
Only one statement should be uncommented.
Example: CLKIN is a 20MHz crystal.
In step 1 the user specified PLLCR = 0xA for a
100Mhz CPU clock (SYSCLKOUT = 100MHz).
In this case, the CPU_RATE will be 10.000L
Uncomment the line: #define CPU_RATE 10.000L
For a 60 MHz CPU clock (SYSCLKOUT = 60MHz), user
specified PLLCR = 0x06 in step 1.
In this case, the CPU_RATE will be 16.667L
Uncomment the line: #define CPU_RATE 16.667L
-----------------------------------------------------------------------------*/
#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 16.667L // for a 60MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
//----------------------------------------------------------------------------
/*-----------------------------------------------------------------------------
Specify the SYSCLKOUT max frequency for examples - either 60 MHz
(for 60 MHz devices only) or 100 MHz (for all other devices - this is
the default SYSCLKOUT frequency for all examples).
Doing so will allow the debugger to compile Example code which is dependent
upon CPU frequency for that frequency.
Example: CLKIN is a 20MHz crystal.
In step 1 the user specified PLLCR = 0xA for a 100 MHz
CPU clock (SYSCLKOUT = 100MHz).
Then #define CPU_FRQ_100MHZ is set as 1 (default) and
#define CPU_FRQ_60MHZ is set as 0 (default).
If PLLCR = 0x06 in step 1, then:
#define CPU_FRQ_100MHZ is set as 0 and
#define CPU_FRQ_60MHZ is set as 1.
-----------------------------------------------------------------------------*/
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq - default, 1 for 100 MHz devices
#define CPU_FRQ_60MHZ 0 // 60 MHz CPU Freq - 1 for 60 MHz devices
//---------------------------------------------------------------------------
// Include Example Header Files:
//
#include "DSP280x_GlobalPrototypes.h" // Prototypes for global functions within the
// .c files.
#include "DSP280x_ePwm_defines.h" // Macros used for PWM examples.
#include "DSP280x_I2C_defines.h" // Macros used for I2C examples.
#define PARTNO_28016 0x14
#define PARTNO_28015 0x1C
#define PARTNO_2809 0xFE
#define PARTNO_2808 0x3C
#define PARTNO_2806 0x34
#define PARTNO_2802 0x24
#define PARTNO_2801 0x2C
// Include files not used with DSP/BIOS
#ifndef DSP28_BIOS
#include "DSP280x_DefaultISR.h"
#endif
// DO NOT MODIFY THIS LINE.
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L)
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP280x_EXAMPLES_H definition
//===========================================================================
// End of file.
//===========================================================================
Regards,
Frederic
