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TMDSECATCNCD379D: Phase shift problem between sync0 signal and MCU's own PWM signal

Part Number: TMDSECATCNCD379D
Other Parts Discussed in Thread: C2000WARE

Hi there, my first post on this forum :D

We are developing servo motor control and have roughly integrate ethercat slave stack code example with our existing motor control code for testing. 

As we dig deeper we found that there is a slow phase shift between sync0 interrupt and MCU's own PWM interrupt signal. 

The shift is causing problem to our applicaiton. We can move the position control loop to sync0 isr but we relied on a 8000Hz PWM for voltage and current control, out of sync between them will cause wired movement on motor.

So our question is, is there any way to control the phase shift? Can it be solved on software level or the hardware need to be modified?

Also we are puzzled, we have study the ethercat slave refernce design TMDSECATCNCD379D, there is no clock sync design within, but they must have the same problem for ethercat application right? Then how they do it?

Thanks for reading, any reply is greatly appreciated

  • Hi

    Assume, we are comparing an PWM event interrupt (like some CMPA match) and sync0 event.

    Do you see a fixed phase shift between the PWM interrupt and sync0 pulse or drift?

    Since the sync and PWM are separate events, they are expected to have some delay. There will be sync0 jitter as this is generated by the Ethercat master update rate. Check the update rate of Ethercat master and or Master PC/PLC loading for the master to behave deterministically.

    TMDECATCNCD379D, uses external ET1100 Ethercat slave device that runs on its own clock, not based on F29379D controller/PWM clock.

    Both these systems should behave identical.

    Additionally, since PWM interrupt is based on CMP event, you can adjust compare event value to match your need. This can help only a fixed delay not any drift.

    thanks

    Sam

  • Thanks for the reply Sam!

    The phase shift is not fixed, it slowly drift apart as time goes. I tried to illustrate it in the oscillogram below:

    red line represent sync0 interrupt, blue line represent PWM interrupt. On the left in yellow circle, sync0 interrupt happened right after PWM interrupt, but after ~100ms, on the right in green circle, sync0 happened much latter (drift to right) compare to PWM interrupt.

    We are looking into measuring the drift between sync0 and PWM then adjust PWM accordingly to accomodate sync0. Is there any good way to do this?

  • HI

    TMDSECATCNCD379D, is a two chip solution, F28379D + ET1100. You can sync the F28379D PWM events with Sync0 pulse event, either in hardware or Software. Enable EXTSYNC1 signal pin to Sync0 pulse or initiate a SWFSYNC (PWM register bit in TBCTL) on any Sync0 based interrupt in the MCU.

    Hope this helps

    Thanks

    Sam

  • Thanks Sam, we have tried out the first method you suggested with the following code:

    1. Assigned EXTSYNCIN1 to GPIO86

    InputXbarRegs.INPUT5SELECT = 86;

    2. Modified PWM setting to use EXTSYNCIN1 as sync signal

    before modification:
    3 pwm setting:
    EPwm1Regs.TBCTL.bit.PHSEN    = TB_DISABLE;	//master
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
    EPwm2Regs.TBCTL.bit.PHSEN    = TB_ENABLE;	//slave
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	// sync "down-stream"
    EPwm3Regs.TBCTL.bit.PHSEN    = TB_ENABLE;	//slave
    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	// sync "down-stream"
    
    after modification:
    3 pwm setting:
    EPwm1Regs.TBCTL.bit.PHSEN    = TB_ENABLE;	//slave
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	//for external IO
    EPwm2Regs.TBCTL.bit.PHSEN    = TB_ENABLE;	//slave
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	// sync "down-stream"
    EPwm3Regs.TBCTL.bit.PHSEN    = TB_ENABLE;	//slave
    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	// sync "down-stream"

    3. Unfortunately from our observation this doesn't work, PWM is shifted in a way it happened just before or after the sync0 signal. So we tried to further adjust PWM phase at every sync0 interrupt:

    EPwm1Regs.TBPHS.bit.TBPHS = EPwm1Regs.TBCTR+(temp2);
    EPwm2Regs.TBPHS.bit.TBPHS = EPwm1Regs.TBCTR+(temp2);
    EPwm3Regs.TBPHS.bit.TBPHS = EPwm1Regs.TBCTR+(temp2);

    with temp2 being a compensation value. It is calculated based on the time difference between sync0 and PWM happened just before it. This time it worked fine, the 2 signals finally in sync!

    But we are puzzled why the phase compensation are needed. Both from you and reference guide the first 2 steps should be suffice for synchronization. Did we missed something? Or is it becasue sync0(1000Hz) and PWM(8000Hz) are in different frequency so the EXTSYNCIN1 doesn't work?

  • Hi

    Since we do not see the full context of your firmware, we do not have an immediate answer. Glad you have a way to make this work.

    Will revert back after few reviews with our engineers. Please anticipate some delay in the reply

    Thanks

    Sam

  • Hi

    Additionally to understand your hardware, please check if it works when you use SWFSYNC, inside Sync0 based interrupt routine, or any external asynchronous signal.

    thanks

    Sam

  • HI

    Hope you were able to test the SWFSYNC functionality.

    Also try the SW example referenced below in the tools to check if your hardware is working with external trigger.

    Please update the status for further follow ups, if needed.

    Thanks

    Sam

    C:\ti\c2000\C2000Ware_2_00_00_03\driverlib\f2837xd\examples\cpu1\epwm

    epwm_ex3_synchronization

  • Thanks for the reply Sam!

    We will definitely check out the example.

    We haven't test on SWFSYNC, will post an update if we get around on that

  • Hi

    Understand, please update us once you have some test data.

    Hope this helps at this time.

    thanks

    Sam