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CCS/TMS320F28379D: The time base fo CLB

Part Number: TMS320F28379D

Tool/software: Code Composer Studio

Hi all

As shown in the picture above, clock period is 20nS, sim_duration is 50000ns, reset_duration is 40nS.

Whether the Clock Frequency of CLB Hardware is specified by "clock_period"? Can it be adjusted? What is the adjustment range?

In addition, no reset signal can be observed during simulation. That doesn't seem too good.

In the above tow pictures, reset time is 40ns, out0(red line) stage change moment is 10uS. So, 40ns + 10uS = 10040ns.

I hope you can help to judge the cause of the problem. If you need to provide some information, please let me know.

Best Regards

  • Hi,

    Note that the frequency you set here is only used for simulation.
    When you port the logic to the hardware - the clock configuration has to be done separately, in the same way you would configure clock for other modules.
    CLB can operate at 100MHz maximum frequency.
    You can refer to any of the examples to see the clock configuration.
    Specifically, regarding the above question - you can change the period to any value from 20ns, and rebuild the project and reload the .vcd, you'll see the updated clock frequency. But it's of no consequence to the hardware hence I suggest no need for changing this parameter for simulation, for your case.
    Also, The reset is held low initially for the defined duration 40ns. You can look at the very beginning of the simulation from 0 to 40ns.

  • Dear Subrahmanya

    Thank you for your help.

    As you mentioned "CLB can operate at 100MHz maximum frequency", where does it come out in datasheet?

    Is it mean that there is a "/2" devider in the clock path?

  • Hi,

    On F28379D CLB is on same clock as EPWM. There is  a divider (EPWMCLKDIV).
    You are correct - It is not very obvious from the documentation. I'll submit feedback for documentation update.
    Thank you.