Part Number: TMS320F28379D
Tool/software: Code Composer Studio
Hi all
As shown in the picture above, clock period is 20nS, sim_duration is 50000ns, reset_duration is 40nS.
Whether the Clock Frequency of CLB Hardware is specified by "clock_period"? Can it be adjusted? What is the adjustment range?
In addition, no reset signal can be observed during simulation. That doesn't seem too good.
In the above tow pictures, reset time is 40ns, out0(red line) stage change moment is 10uS. So, 40ns + 10uS = 10040ns.
I hope you can help to judge the cause of the problem. If you need to provide some information, please let me know.
Best Regards


