F28M36P63C2: Parallel operation of inverters

Hi,

Are both inverters switching at same PWM frequency and in synchronization all the time?
Is it possible that the instance you are trying to read the voltage there is noise due to switching on the other inverter (in this case inverter 1)?

Alexandros Paspatis said:

i want to synchronize the second inverter ( inverter 2)

Alexandros Paspatis said:

Maybe the problem is related to the fact that i use the ePWM ADC SOCA for triggering the ADC inputs.

Hi, 

Thanks for your reply.

Both inverters operate at the same switching and sampling frequency.

The same exactly code is run on 2 different computers, one for each microcontroller of each inverter.

Since the first inverter is initially operating alone (with the load), what i am trying to do is to synchronize the second inverter on the existing power system ( consisting of the inverter 1 and the load). The voltage read is very good but every 10-15s it gets seriously distorted so i have not tried to synchronize them yet.

If the noise was coming from the switching of inverter 1, wouldn't it be permanent?

What do you mean be synchronizing the PWMs?

The noise does not exist neither in the probed voltage nor in the 0/3V output of the sensor. It only exists in the CCS graph where i read the ACD output value from my code. So it seems that it is initiated in the ADC conversion.

I am using an event trigger at EPWM2A, at first event with CTR=ZERO and CTR=PERIOD. I also tried using only CRT=ZERO or CTR=PERIOD and second event start.

I hope i answered your questions. Let me know if you need anything else.

Alex

Hi,

1. PWM outputs can be synchronized. Even if they are on 2 different microcontrollers, you can send a synchronization input from one MCU to another.
Please refer to "Figure 7-7. Time-Base Counter Synchronization Scheme 4" of device TRM. This allows a GPIO signal to be used an a synchronization input.
One MCU can generate EPWMxSYNCO and can be connected to another MCU as EPWMxSYNCI.

2. Since you mentioned that there is no noise in the measured signal - when plotted on the scope, but noise only exists in the CCS graph, i'm wondering if its a graphing issue. Is there a possibility that the graph buffer is being overwritten with some other data? any Overflow in data captured?
Also, please cross check your graph properties and make sure that the buffer settings etc. are accurate.

Alexandros Paspatis said:

The noise does not exist neither in the probed voltage nor in the 0/3V output of the sensor. It only exists in the CCS graph where i read the ACD output value from my code. So it seems that it is initiated in the ADC conversion.

Many thanks for the reply.

I dont think its point 2 for 2 reason:

1) When i operate the inverter in stand-alone (if i just connect inverter 2 to the load) everything works perfect. There is no noise and the graph is clear with exactly the same settings.

2) The output of the ADC is connected to some protection logic system which in case of an overvoltage for example would open the relay. When trying to read the voltage in the synchronisation case, this protection system is enabled. Thus, this noise exists in the actual output of the ADC and does not come up in the graph only.

Using a connection between the MCs would be a strict requirement. Can't i manage to read the voltage accurately without this? Is the problem indeed due to the triggering coming from the PWM?

Let me know if you have any more insight after my above comments.

Thanks a lot.

Alex

Hi,

Alexandros Paspatis said:

Using a connection between the MCs would be a strict requirement. Can't i manage to read the voltage accurately without this? Is the problem indeed due to the triggering coming from the PWM?

Hi,

Note that during the synchronisation process, the second inverter is not connected to the load (relays are open). Thus, the probed load voltage is solely produced from the inverter 1. In inverter 1 everything is running smoothly. So, why would you except if there is an issue in the inverter 2 sampling the load voltage to be affected?

I can see 4 full periods of the sine wave voltage in the CCS graph. Every 10-15s, about 8-12 periods are getting heavily distorted (the waveform is not sinusoidal and there are also some spikes). After that the voltage returns to normal. And again after 10-15s, the same thing happens.

I hope that helped.

Alex

Hi,

We also sent the voltage after the adc into an ecap module and pictured it in the oscilloscope. The same problem persists. So for sure it is not an issue of the memory or the graph.

Alex

Hi,

Alexandros Paspatis said:

We also sent the voltage after the adc into an ecap module and pictured it in the oscilloscope. The same problem persists. So for sure it is not an issue of the memory or the graph.

Alexandros Paspatis said:

The noise does not exist neither in the probed voltage nor in the 0/3V output of the sensor. It only exists in the CCS graph where i read the ACD output value from my code. So it seems that it is initiated in the ADC conversion.

You've confirmed 2 things.
1. These is no noise in the sensed signal going into ADC.
2. Noise reflects on ADC results and observed via graph as well as other methods (eCAP).

Is there any noise on the other inputs (like Vref hi/lo, power supply, IO switching?) coinciding with noise?

I would also refer to ADC experts. 

Hi,

Yes i have confirmed both.

Furthermore, i tested the ADC ouput without the low pass filter that i was originally using. It seems that every 15s, big spikes occur at the sinusoidal form (the voltage was around 20Vac and the spikes were around 300V). The same spike was observed at 50Vac as well.

Note that this spike does not exist at the output of the voltage sensor.

Both microcontrollers are connected through 2 USBs (each one) to each computer.

Can you understand anything more according to these? Aren't there ADC experts in TI that could take part in the discussion?

Thanks.

Alex

Hi,

Alexandros Paspatis said:

Can you understand anything more according to these? Aren't there ADC experts in TI that could take part in the discussion?

Thanks a lot! 

Note that i have figures and videos that i can share with you to help you through e-mail or skype.

Alex

Update: 5V to GND pins were probed. The uController power supply seems really stable and without any spikes.

Alex,

Picking up for Bharathi on this topic.  There is some clarification I'd like to make after reading through the thread.

1)I'll send you a friend request through the E2E system. We can use that to share files/scope plots privately as you mentioned.  If possible I'd like to see the schematic if you are comfortable sharing.  If you can share just the MCU relevant pages that would be fine as well.  I'd also like to know the PN for the protection device(this may be in the schematic anyway), as well how the two MCUs co-exist in your system, i.e. isolated from one another, etc.

2)Have you measure the output of the voltage sensor at the ADC pin or just at the voltage sensor itself?  It is very possible we are picking up noise on the trace and the signal is not the same.

3)You mentioned that using the eCAP yields the same results as the ADC, I inferred you mean you also see the noise on this route as well.  Can you confirm this?

4)You last post mentioned observing a clean 5V/GND for the chip that give the uC supply.  Can you also look at the 3.3V and 1.8V rails and VREFLO/VSSA signals at the C2000 MCU specifically the analog supply pins?  VREFLO inside the ADC is tied to VSSA, so any ground movement will result in a change in a converted voltage input, even if the input signal is clean

I think the above is a good start, we can go deeper once I have some of the above info.

Best,

Matthew

Hi,

Thanks a lot for you time.

1) I have share information privately. I am waiting for your response.

2) The output of the sensors is connected to a ribbon. The ribbon ground is connected to the microcontroller ground. I measured the sensor's output pin of the ribbon with regards to the uC ground using a differential voltage probe. Some noise exists in the oscilloscope after 1Mhz but the same noise exists in the 1st inverter (connected) as well which does not exhibit this problem.

3) Confirmed!

4) I ll test the 3.3V. Where can i find the 1.8V rail?

Thanks.

Alex

Hi,

Any update?

Alex

Alex,

Q4) I ll test the 3.3V. Where can i find the 1.8V rail?

A4)You'll need to look at the VDD18 pins for this, although after thinking about this some more, I doubt these are causing any issue.  The important thing is that VDDA# pins and VSSA# pins are clean.  VSSA# will also act as the ground reference point for the ADCs.

Back to the issue with the noise coupling.  From my experience it is often best to place the ADC sample as near the swithcing point of the PWMs to get the max/min voltage levels and a true capture of the system.  However, the switching point of the PWMs is often the noisest condition in a digital power system so we run the risk of sampling that noise into our ADC.

The observance of the noise coming and going, could either mean we are right on the edge of this switching event with our ADC sample and we "beat" in and out of this over time(which would indicate some amount of sampling jitter); or some element of the topology is coming online only under certain conditions then going away, coming back, etc.

I would guess we are seeing the former, but you could comment based on what your code is doing if the latter is the case.

We can try and move the ADC trigger away from this consistently, but to do so I think you will need to bring another PWM online.  In this case the new PWM could be a mirror of the existing one that is controlling the FETs, but place your compare value a few cycles prior to trigger the ADC earlier.  We can keep moving this around to see if we can find a "safe" zone for all conditions.  The drawback here is that the ADC sample won't be as close to the switch in time so there may be some loss in information we get back.

Another alternative would be to see if we can observe this "noise" getting coupled to the signal or VDDA/VSSA pins and try and damp it/filter it.  This could be some added capacitance near/at the pin.  Something else to check in general is that all decoupling caps you alreay have are as physically close to the device as possible.  This will help reduce the amount of radiated noise we might pick up from the power electronics.

Look forward to your thoughts on the above.

Best regards,

Matthew

MatthewPate said:

We can try and move the ADC trigger away from this consistently, but to do so I think you will need to bring another PWM online.  In this case the new PWM could be a mirror of the existing one that is controlling the FETs, but place your compare value a few cycles prior to trigger the ADC earlier.  We can keep moving this around to see if we can find a "safe" zone for all conditions.  The drawback here is that the ADC sample won't be as close to the switch in time so there may be some loss in information we get back.

Hi,

Can you please explain me how to do this on the simulink support package? I already have 3 pwm's (one for each leg). Should i add a 4th with the same switching frequency and just initialise it somewhere else?

Thanks.

Alex

Hi,

We tried by creating a 4th PWM block with exactly same settings as the other 3. We just changed the CMPA, which instead of coming from an input it was now specified via dialog. We tried many CMPA values inside our timer period range (i.e. 0-4687) and nothing changed. We had exactly the same issue.

I have also sent you some extra information in a personal message.

Let me know if you have any other idea.

Thanks.

Alex

Following up from off forum, would it be possible to add a coupling capacitor across the isolated ground planes in order to provide a ground path for any noise coupling occuring between the two?  Will add others to the chain as well for their input.

Best,

Matthew

Hi,

Could your please give me more details regarding the connection points of the capacitor and the nature  of the required capacitor?

Thanks a lot.

Alex

You will probably need some Y-caps for common mode noise filtering.

Two micro-controllers controlling the two inverters have their own GND at negative DC bus (BUS-). These GNDs could be at different levels with respect to CHASSIS GND because of CM noise. So when they are measuring the same output voltage at the common connection point the CM noise can corrupt the ADC measurements. By adding Y-caps you can suppress these CM noise. Pls see the attached doc for a discussion on this.

ShamimY_caps.pdf

Thanks for the reply.

Could you please give me specification of the Y-caps needed (type and capacitance) for the controller under discussion and their connection point?

I 'll check the attached document as well.

Alex

You probably need some Y caps to filter common mode noise in the system. Since the two inverters measure the same output voltage their GND ref have to be at same potential. But because of CM noise they could be different with respect to CHASSIS ground. Adding Y-caps between individual GND and CHASSIS ground will filter those CM noise effect. Attached is an article on this for your reference.

Shamim1104.Y_caps.pdf

You probably need some Y caps to filter common mode noise in the system. Since the two inverters measure the same output voltage their GND ref have to be at same potential. But because of CM noise they could be different with respect to CHASSIS ground. Adding Y-caps between individual GND and CHASSIS ground will filter those CM noise effect. Attached is an article on this for your reference.

Shamim3187.Y_caps.pdf