TMS320F28069: SOLAR 3 Phase SPLL Lock Phase Problem

İlker

Part Number: TMS320F28069

Hello All,

I am trying to use SOLAR Library V1.2 SPLL_3ph_SRF with ABC_DQ0_POS with Control-Law Accelerator.
ABC/DQ0 Transforms's Q value is fed to the SPLL_3ph_SRF and the Theta Output of the SPLL is used to calculate the sin/cos values as shown in the library user guide.

Three-Phase Input Voltage is coming from the grid as follows;
Line1 Vsin(wt)
Line2: Vsin(wt-120)
Line3: Vsin(wt+120)

For the variable " ABC_DQ0_POS_CLA V_Frame "

V_Frame.a = Line1
V_Frame.b = Line2
V_Frame.c = Line3

With this configuration of "A-B-C == L1-L2-L3" , SPLL Locks to Line2(theta output is between 0-2pi and following the L2)
If I change the Configuration as "C-A-B == L1-L2-L3" now it Locks to L3 and for "B-C-A == L1-L2-L3" SPLL locks to L1. (Seems like SPLL Locks whichever B holds)

After the SPLL, there are some control-loops controlling D,Q and Z Components of the Current that is also subjected to ABC/DQ0 Transform which uses the theta information obtained from above.

So I was wondering if it is Okay to use the A-B-C Configuration for the Currents and use the theta obtained from the SPLL with B-C-A Configuration ? And if thats not a valid solution What Should I be doing here ?

Also, I have tried to use ABC_DQ0_POS_CLA_MACRO to transform the input voltages and then DQ0_ABC_CLA_MACRO to obtain the initially given input voltages back from the transformation. I observed a Phase Difference between the Input Voltages and the Output of the DQ0/ABC Transform, I was thinking they should be matching.

Any help would be appreciated, Thanks in Advance, İlker.

over 4 years ago

0 Manish Bhardwaj over 4 years ago

TI__Mastermind 43730 points

Hi, we use a cosine based DQ transform in the code, i.e. you will see -90 degree at zero crossing point of the sine wave. (https://www.mathworks.com/help/physmod/sps/powersys/ref/abctodq0dq0toabc.html)

0 İlker over 4 years ago in reply to Manish Bhardwaj

Intellectual 290 points

Hello again Manish

I am posting the waveforms I have Observed:

Upper-Most shows the Line-1 Voltage Waveform,
One in the middle is (Theta*100)
And the one in the bottom is What I get after "Lines --> ABC/DQ --> DQ/ABC " Transform Pair.

What I feel is ABC/DQ -- DQ/ABC Transform Pair works OK for the given theta, but it seems like PLL Locks with a Theta about 30 degrees of Phase Shift.

What I Understand from your previous Answer is to expect "V* cos(wt + theta)" at the Line1, Am ı Missing Something Here ?

I Thank you again, İlker

0 Manish Bhardwaj over 4 years ago in reply to İlker

TI__Mastermind 43730 points

Hi,

I see your Vac has DC offset, you need to make sure the Vac ranges from +1 to -1, this is typically achieved by doing

(ADC_Read * 1.0f/4096.0f -0.5f)*2.0f

0 İlker over 4 years ago in reply to Manish Bhardwaj

Intellectual 290 points

Hello Manish,

I checked the signals on the PCB, there I saw PLL Locks to the Line as it should be, so I am not experiencing the problem any longer.

--------------------------------------------------------------------------------------------------------

The Graph above is the graph of the raw adc readings that are carried to some spesific Memory Location by DMA. I actually normalize them before using with the SOLAR Library.

Yet, -strange in fact- What I see from the debugger is as the graphs I shared above. I was thinking maybe the cause of the phase lag I observe is the time that it takes for the DMA to carry the data.

Thank you for your concern, Have a nice day, İlker.

0 Manish Bhardwaj over 4 years ago in reply to İlker

TI__Mastermind 43730 points

glad the issue is resolved.

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TMS320F28069: SOLAR 3 Phase SPLL Lock Phase Problem