This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28069: Questions regarding F28069 type 3 ADC's smapling and conversion time

Part Number: TMS320F28069

Hi expert,

My customer would like to optimize F28069's ADC performance and may need to get some details out of datasheet or TRM from you.

In below diagram:

F28069 do simutaneous sampling and may need to convert two S/H circuits' output. In this case, it will take 26 ADCCLKs to convert and get result. How does the conversion circuit work? It there any way to reduce the conversion time by overlaping some part of the conversion process?

Similarly, will it be able to overlap the session "conversion 0" and "conversion 1" in below use case?

Thanks

Sheldon

  • Sheldon,

    In terms of simultaneous sampling the benefit on this device is to overlap the voltage sampling portion of the ADC process (as shown in the 7 ADC Clock time bar).  Since there is only one ADC the physical conversions of the samples are sequential as shown in the timing diagram.  The state of the pins in the time domain, i.e. the voltage captured, will be correct.

    Now, if the customer has more samples to take, the next voltage sampling period will take place 7 cycles before the current conversion is complete.  This will be true of any future sample as long as the converter is running.  This is like a pipeline effect on a CPU, where we take advantage of unused circuitry(in this case the sample and hold) even though the current conversion is complete.   Just like a pipeline, however, there is no benefit when the ADC is started from idle state.

    Best,

    Matthew

  • Hi Matthew,

    Need to check a few more details with you. In Figure 8-34 condition.

    1. In the second SOC's sample + conversion, if sample window increased from 7 clock cycles to 10, will the sample window starting from point A to B?

    2. If the sample window of the second SOC goes beyond 13, such as 15, will the conversion starging from something like point D?

    3. BTW, how long do the S/H circuit make connection with the conversion circuit electrically? Does this electrical connection persisting the whole conversion clocks?

    4. Will the errata case "ADC: Initial Conversion" related to uncertain S/H window on first conversion? If not, how was that caused?

    Thanks

    Sheldon

  • Answers inline: 

    1. In the second SOC's sample + conversion, if sample window increased from 7 clock cycles to 10, will the sample window starting from point A to B?

    A1)Yes, the conversion process will not begin until the sample is complete, so in this case the conversion0 would be delayed by 3 ADC Clock cycles

    2. If the sample window of the second SOC goes beyond 13, such as 15, will the conversion starging from something like point D?

    A2)As it is in the diagram the conversion for the second SOC starts immediately after the first SOC finishes since the sample for conversion 2 takes place during the last 7 cycles of the first conversion.  If the S/H duration for the second sample is >7 ADC Clocks then the second conversion will be delayed by whatever in excess of 7 Clocks is selected.

    3. BTW, how long do the S/H circuit make connection with the conversion circuit electrically? Does this electrical connection persisting the whole conversion clocks?

    A3)The connection is only for the time specified in the ADC_ACQPS register setting.  In the above diagram the S/H circuit is only closed for 7 ADC Clock cycles shown above

    4. Will the errata case "ADC: Initial Conversion" related to uncertain S/H window on first conversion? If not, how was that caused?

    A4) The errata on the initial conversion is related to the state of the converter itself when it is unused.  Once there is a sample taken the converter is always in a known state so that the next conversion is not impacted.

    Best,
    Matthew

  • Hi Matthew,

    Thanks for your detailed answer here. But, I'd like to move a bit more on your answers,

    1. In the second SOC's sample + conversion, if sample window increased from 7 clock cycles to 10, will the sample window starting from point A to B?

    A1)Yes, the conversion process will not begin until the sample is complete, so in this case the conversion0 would be delayed by 3 ADC Clock cycles

    I'd like to know here is the SOC 2 will have a chance to increase the sample window longer (to up to 13 ADCCLKs) wihtout delay the "conversion 1" here. Is that right?

    2. If the sample window of the second SOC goes beyond 13, such as 15, will the conversion starging from something like point D?

    A2)As it is in the diagram the conversion for the second SOC starts immediately after the first SOC finishes since the sample for conversion 2 takes place during the last 7 cycles of the first conversion.  If the S/H duration for the second sample is >7 ADC Clocks then the second conversion will be delayed by whatever in excess of 7 Clocks is selected.

    If SOC 2's sample window increased to 10 ADCCLKs, will it start earlier such as starting from point A and not delay the "conversion 1"?

    3. BTW, how long do the S/H circuit make connection with the conversion circuit electrically? Does this electrical connection persisting the whole conversion clocks?

    A3)The connection is only for the time specified in the ADC_ACQPS register setting.  In the above diagram the S/H circuit is only closed for 7 ADC Clock cycles shown above

    I mean the connection time after the sample and hold is finished. In this case, S/H capacitor will be connected to the conversion circuit. But how long will they be connected together?

    Thanks

    Sheldon

     

     

  • Hi Matthew,

    Thanks for your detailed answer here. But, I'd like to move a bit more on your answers,

    1. In the second SOC's sample + conversion, if sample window increased from 7 clock cycles to 10, will the sample window starting from point A to B?

    A1)Yes, the conversion process will not begin until the sample is complete, so in this case the conversion0 would be delayed by 3 ADC Clock cycles

    I'd like to know here is the SOC 2 will have a chance to increase the sample window longer (to up to 13 ADCCLKs) wihtout delay the "conversion 1" here. Is that right?

    A1.1)That is correct, the next S/H window length doesn't effect the conversion time of the previous sample; in isolation there will always be 13 ADC Clock between the end of the S/H phase and the conversion complete.

    2. If the sample window of the second SOC goes beyond 13, such as 15, will the conversion starging from something like point D?

    A2)As it is in the diagram the conversion for the second SOC starts immediately after the first SOC finishes since the sample for conversion 2 takes place during the last 7 cycles of the first conversion.  If the S/H duration for the second sample is >7 ADC Clocks then the second conversion will be delayed by whatever in excess of 7 Clocks is selected.

    If SOC 2's sample window increased to 10 ADCCLKs, will it start earlier such as starting from point A and not delay the "conversion 1"?

    A2.1)No, the soonest the next S/H window can start is 6 ADC Clocks after the previous conversion has started.  At this point the S/H logic will be free to sample while the current conversion completes.

    3. BTW, how long do the S/H circuit make connection with the conversion circuit electrically? Does this electrical connection persisting the whole conversion clocks?

    A3)The connection is only for the time specified in the ADC_ACQPS register setting.  In the above diagram the S/H circuit is only closed for 7 ADC Clock cycles shown above

    I mean the connection time after the sample and hold is finished. In this case, S/H capacitor will be connected to the conversion circuit. But how long will they be connected together?

    A3.1) I understand better now, this is related to my answer A2.1, the S/H circuit is still in use for the first 6 ADC clock cycles of a conversion, after that it is free to start the next sample.

    Thanks

    Sheldon