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TMS320F28377D-EP: Atomic data types

Miroslav Prudky
Intellectual 260 points
Part Number: TMS320F28377D-EP


Hello,

1) I'm wondering whether some of the official TI documentation explicitly states, which of the C-data types ensures the accesses to variables of such types are atomic ?

2) Please confirm my expectations. I expect that variables of the following data types are always read and/or written atomically:

- 16bit integers

- 32bit integers

- 32bit floats

  • 0
    TI__Guru* 92770 points

    Hello Miroslav,

    The C language does not have a keyword/construct for "atomic" operations.   There is no guarantee that the compiler will generate a single atomic instruction for operations on any data type.

    For AND/OR/XOR etc.. You could make use of a few compiler intrinsics that map directly to the assembly read-modify-write instructions (__and, __or and __xor - documented in www.ti.com/lit/SPRU514).

    If you have a segment of code that needs to be atomic, then you need to disable and enable interrupts around the code.  (There are intrinsics to do this documented in the same user's guide).

    If the segment is in an ISR, then interrupts are automatically disabled when the interrupt is entered and remain so until they are re-enabled by the application.


    Regards
    Lori

  • 0 in reply to Lori Heustess
    TI__Guru* 92770 points

    Additional note: if you search for the word "atomic" in The Compiler's User's Guide (http://www.ti.com/lit/spru514 ) you will find other intrinsics that behave in an atomic manner. 

    Regards

    Lori

  • 0 in reply to Lori Heustess
    Intellectual 260 points

    Lori,

    thanks for the answers.

    Asked a different way: 16-bit and 32-bit accesses (read, write) to the memory and registers are executed as an atomic (1 cycle) instructions, correct ?

    Regards,

    Miroslav

  • 0 in reply to Miroslav Prudky
    TI__Guru* 92770 points

    Miroslav,

    If the access is performed with a single assembly instruction, and that instruction makes it to the decode 2 phase of the pipeline, it will complete before the interrupt is serviced.  If it is before the decode 2 it will be discarded and re-fetched after the interrupt returns. 

    If the access involves two instructions, then an interrupt could come between the two. 

    Regards

    Lori