TMS320F28374D: not able to boot CPU2 when running both cores

Dear Carlo,

Thanks for reaching out to us regarding your project based on the TMS320F28374D.  Looks like you are close because the individual applications for CPU1 and CPU2 are working properly.

 Please do take the time to do a detailed study of this excellent training material available here:  https://training.ti.com/c2000-f2837xd-microcontroller-workshop?context=1137755-1139641-1137781  

I encourage you to study the entire training material but you could focus on Chapter 4: Reset and Boot Process in  the TMS320F2837xD Microcontroller Workshop Manual.

Please reach back out to us if you have further questions after studying the training material.

Cheers!

Krishna  

Hi Krishna , 

pelase I read all papers ad C2000ware examples are working .

my problem is apparently I did everything ok but I m stuck , so somthing is wrong .

do you see anything wrong in my previous screenshots ? anything I shoudl change /test to  see where am I wrong ?

thank you 

bets regards

Carlo

Hi Carlo, 

Can you elaborate a bit more on your following comment:

    --- Leaving the system and CPU1 run, I get this error due to wrong location:   ( see pitcure 3 attahced ) 

Cheers!

Krishna

Hi Krishna , 

if I let the CPUs run  I can see CPU2 going in wrong location , while CPU1 stays in while forever  waiting to cpu2 .

quite likely something is missing in CPU2 settings . ( The two app if no jump to app , so relocated fully works on both CPUs ) 

what woudl help me a lot is an example with boot on CPU1 , boot on CPU2  and relatives jump to app ( boot can be dummy code in the example ) .  I see in C2000ware  example with app on both side but not  boot + jump to application 

I can share files offline if needed

thank you 

best regards

Carlo

HI Krishna , 

we did more debug and found the issue is the intercomm flag  if I disbable the while(IpcRegs.IPCSTS.bit.IPC0 == 0);   the two CPUs  jumps correctly and work  .  

hereunder you can see the point . 

please where am I wrong ?  what shoudl I check ?  I can share code offline 

CPU1                                             |                                         CPU2

CORE_OwnerConfig();                 |                                         // Flag to CPU01 that the variables are ready in MSG RAM with CPU02 TO

IpcRegs.IPCSET.bit.IPC0 = 1;       |                                        // CPU01 IPC Flag 17

#if defined(_RELEASE)               |                                          //

IPCBootCPU2(BOOT_FROM_FLASH);       |                        while(IpcRegs.IPCSTS.bit.IPC0 == 0);

#endif                               |                                                     IPCRtoLFlagAcknowledge(IPC_FLAG0);

thank you 

best regards

Carlo

Hi Carlo, Can you please confirm that you are Flash boot mode.  If yes, please let us know how you have configured the device for Flash boot. Regards, Krishna

Hi Krishna 

yes it is confirmed .   any suggestion ?

thank you 

regards

Carlo

Hi Carlo, 

Thanks!  I am consulting with my local domain experts here.  I will get back to you today.  Cheers! Krishna

Hi Carlo, 

In regards to this statement "while(IpcRegs.IPCSTS.bit.IPC0 == 0);"  on CPU2, what is your purpose for this type of coordination between CPU1 and CPU2?.  As you may already know, while CPU1 runs through what you have upto the point of "IPCBootCPU2(BOOT_FROM_FLASH)", CPU2 has only executed the BootROM code and is essentially waiting for an action from CPU1. 

Now when CPU1 issues calls the  IPCBootCPU2(BOOT_FROM_FLASH) API, CPU2 gets out of the BootROM and runs its application.  So it would be better if the application on CPU2 sets the IPC0 bit and CPU1 spins on  while(IpcRegs.IPCSTS.bit.IPC0 == 0); When CPU2 sets that bit then CPU1 will break out of the while and essentially know that CPU2 is running the application.  Does that make sense?

To give you a brief background,  calling IPCBootCPU2(...) API effectively results in the generation of an interrupt on CPU2, with bits 31 and bit 1 set in the CPU01 to CPU02 IPC flag register.  The resulting interrupt handler that runs on CPU2 will clear those bits.  At this point, the statement while(IpcRegs.IPCSTS.bit.IPC0 == 0); will never see the bit set (already cleared by the ISR on CPU2), so it will just be stuck at the while.  We think this is what you may be running into.  

You may have other reasons for your implementation...if so please advise. 

Lastly, you can look at the implementation of the API you are using and related support such as the interrupt handler via C2000Ware. 

<c2000Ware_installation>\device_support\f2837xd\common\source\F2837xD_Ipc_Driver_Util.c

<c2000Ware_installation>\libraries\boot_rom\f2837xd\revB\rom_sources\F2837x_bootROM\cpu02-bootROM\source\c2core_bootrom_interrupts.c

Hope this helps!  Please let us know if this resolves your issue, or if you have further questions. 

Cheers!

Krishna