I'm working with a customer to troubleshoot some issues they are seeing on the MISO line of SPIA in slave mode. It appears that the internal SPIA state machine is occasionally skipping bits when a specific system transient occurs.
In the course of looking into this issue, we have had a look at the layout. It turns out that the layout of the ground with the decoupling caps on VDD and VDDIO is quite bad, with very large unintended loop paths.
We are trying to identify some specific rework to shorten the loop path of these capacitors to their respective pins ground pins. We are wondering which of the power pins (VDD, VDDIO, and GND) are closest to the SPIA peripheral on the die to focus our efforts.
The customer is using the 56-pin QFN package, and are using the following pins:
- 56 - SCLK
- 42 - SIMO
- 31 - SOMI
- 28 - STE
Also, can we confirm if the SPIA peripheral is powered from the VDD or VDDIO domain internally. I would assume the 1.2V VDD domain, and then level shifted to VDDIO at the pins. The customer application uses the internal LDO for the core and 3.3V for VDDIO.
Thanks,
Stuart
