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TMS320F280049C: SCI channel reset clarifications

Hong En Chew
Prodigy 170 points
Part Number: TMS320F280049C
Other Parts Discussed in Thread: C2000WARE

Hello,

I am working with the SCI driver in F28004x driverlib and have three queries on resetting the data buffers:

  1. Shouldn't the function SCI_resetChannels() in sci.h first clear the SCIRST bit in SCIFFTX before setting it?

    The library function now is:

        //
    // Reset the Tx and Rx Channels
    //
    HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST;

    But I'm thinking it should be:

        //
    // Reset the Tx and Rx Channels
    //
    HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_SCIRST;
    HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST;

  2. What exactly does clearing the SCIRST bit in SCIFFTX do? Does it only clear all data in the TX and RX shift registers and buffers? Or does it also clear all data in the TX and RX FIFO buffers?

  3. The F28004x TRM states that clearing the TXFIFORESET/RXFIFORESET bits in SCIFFTX/SCIFFRX will "reset the FIFO pointer to zero, and hold it in reset". Does this only reset the FIFO pointer without clearing existing data in the FIFO buffers?

I am using C2000Ware 3.01.00.00.

Thank you!

  • 0
    TI__Expert 5240 points

    Hi,

    Hong En Chew said:
    Shouldn't the function SCI_resetChannels() in sci.h first clear the SCIRST bit in SCIFFTX before setting it

    As per TRM SCIRST bit "Write 0 to reset the SCI transmit and receive channels" Hence it should be cleared first before setting it as you rightly observed. 

    Thanks for pointing out. 

     I shall get back to you on the specifics related to question 2 and 3.

    Regards,

    Sudharsanan

  • 0 in reply to Sudharsanan
    Prodigy 170 points

    Ok will edit the sci.h file on my end accordingly.

    Do let me know what you find out regarding questions 2 and 3.

    Regards,

    Hong En

  • 0 in reply to Hong En Chew
    TI__Expert 5240 points

    Hi,

    Sure. I am in discussion with the experts to get clarity on your Q2 and Q3.  

    Regards,

    Sudharsanan

  • 0 in reply to Sudharsanan
    TI__Intellectual 1641 points

    Hello my fellow colleague. I just wanted to say that I have the same question as the OP. 

    Could you please push the bug to the C2000 team?

    Regards, Jiri

  • 0
    TI__Expert 5240 points

    Hi,

    Please find the details for your Q2 and Q3. 

    Hong En Chew said:
    What exactly does clearing the SCIRST bit in SCIFFTX do? Does it only clear all data in the TX and RX shift registers and buffers? Or does it also clear all data in the TX and RX FIFO buffers?

    • Resets Fifo read & write pointers [Both RX & TX]
    • Resets TXFFINT & RXFFINT status
    • Resets RXFFOVF [Overflow status]

    Hong En Chew said:
    The F28004x TRM states that clearing the TXFIFORESET/RXFIFORESET bits in SCIFFTX/SCIFFRX will "reset the FIFO pointer to zero, and hold it in reset". Does this only reset the FIFO pointer without clearing existing data in the FIFO buffers?

    It only resets the FIFO Pointer without clearing the existing data in the FIFO Buffers. The FIFO buffers will be overwritten next time pointer is incremented hence there is no way to read the existing data after doing RESET of the FIFOs.

    Hope it clarifies.

    Regards,

    Sudharsanan

  • 0 in reply to Jiri Panacek85
    TI__Expert 5240 points

    Hi Jiri,

    What is OP here? 

    Jiri Panacek85 said:
    Could you please push the bug to the C2000 team?

    If you are referring to the SCI_resetChannels() API bug discussed here, yes I already filed a bug in our internal bug tracking system to fix it.

    Regards,

    Sudharsanan

  • 0 in reply to Sudharsanan
    Prodigy 170 points

    Thanks Sudharsanan, that is very helpful. Would like to clarify two points:

    1.

    Regarding clearing the SCIRST bit:

    Sudharsanan said:
    Resets Fifo read & write pointers [Both RX & TX]

    Is this functionally equivalent to clearing the both TXFIFORESET/RXFIFORESET bits (but without actually clearing them)? I ran some SCI echoback code on a F280049C device and clearing the SCIRST bit does not clear the TXFIFORESET/RXFIFORESET bits.

    2.

    Sudharsanan said:
    Resets RXFFOVF [Overflow status]

    Noted on RXFFOVF. Can I check if the SCIFFFE/SCIFFPE [FIFO framing/parity error] bits in SCIRXBUF are affected?

    Regards,

    Hong En

  • 0 in reply to Hong En Chew
    TI__Expert 5240 points

    Hi,

    Hong En Chew said:
    Is this functionally equivalent to clearing the both TXFIFORESET/RXFIFORESET bits (but without actually clearing them)?

    Yes it functionally clears them but the Configuration registers are not impacted as per the statement "SCI FIFO register configuration bits will be left as is"

    Hong En Chew said:
    Can I check if the SCIFFFE/SCIFFPE [FIFO framing/parity error] bits in SCIRXBUF are affected?

    Not sure if you are asking if those Error bits are affected by doing SCIRST. Then no, only those I mentioned above are impacted. 

    Regards,

    Sudharsanan

  • 0 in reply to Sudharsanan
    Prodigy 170 points

    Ok that answers my questions. Thanks a lot!

    Regards,

    Hong En