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Compiler/TMS320F280041: Possible bug in F28004x support library for x-bar

Part Number: TMS320F280041

Tool/software: TI C/C++ Compiler

I was going through C28x X-BAR driver, more specifically XBAR_setEPWMMuxConfig() function.

Here is the implementation from xbar.c found in F28004x Support Library v1.06.00.00:

//*****************************************************************************
//
// XBAR_setEPWMMuxConfig
//
//*****************************************************************************
void
XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig)
{
    uint32_t shift;
    uint16_t offset;

    //
    // If the configuration is for MUX16-31, we'll need an odd value to index
    // into the config registers.
    //
    if(((uint32_t)muxConfig & 0x2000U) != 0U)
    {
        offset = ((uint16_t)trip << 1U) + 2U;
    }
    else
    {
        offset = (uint16_t)trip << 1U;
    }

    //
    // Extract the shift from the input value.
    //
    shift = ((uint32_t)muxConfig >> 8U) & 0x7FU;

    //
    // Write the requested muxing value for this XBAR trip.
    //
    EALLOW;

    HWREG(XBAR_EPWM_CFG_REG_BASE + offset) =
        (HWREG(XBAR_EPWM_CFG_REG_BASE + offset) & ~((uint32_t)0x3U << shift)) |
        (((uint32_t)muxConfig & 0x3U) << shift);

    EDIS;
}

Should the "shift" variable in this function be calculated as:

shift = ((uint32_t)muxConfig >> 8U) & 0x0FU;

I may be wrong, but the original mask for shift (0x7FU) won't work for mux 16 to 31. Can someone please check this out?

Thank you!

  • Hi,

     

    Thanks for pointing this out, actually the mask for shift should be (0x1F) since the shift position in the register ranges from 0 to 30 (0x00 to 0x1E). I think the above still works is because when 32-bit number is shifted >31 then it ignores the MSBs of the shift and only lower 5-bit shift is actually used even if the shift has more bits. But I agree that it creates a sense of confusion and also can lead to unpredictable behavior, I will file a bug to get this resolved in the next release.

     

    If my reply answers your question please click on "This resolved my issue" button located at the bottom of my post.

    Regards

    Himanshu

  • You are right, the mask should be 0x1F.

    I am not sure it will work for the following cases from the library:

    XBAR_EPWM_MUX25_INPUTXBAR11 = 0x3201, // shift=0x32 (50)
    XBAR_EPWM_MUX27_INPUTXBAR12 = 0x3601, // shift=0x36 (54)
    XBAR_EPWM_MUX29_INPUTXBAR13 = 0x3A01, // shift=0x3A (58)
    XBAR_EPWM_MUX31_INPUTXBAR14 = 0x3E01  // shift=0x3E (62)

    For all other cases I suppose it works.

    Thank you for your quick answer!