Other Parts Discussed in Thread: C2000WARE
Dear Sir,
we are under development of controler based on 28376s , and have some issue with SPI slave transmit
the spi interface is as follow
1. one unit is configured as SPI Master , send every chuck of 8 SPI word (each 16 bit) (using SPI TX FIFO) - without any interrupt
the slave data is read also from RX FIFO (when the fifo is not empty) , for test purpose the unit sends 8 words of 0xaa55 (this is validated on the slave side)
2.the seconds unit configure as SPI Slave , and every 1ms checks the SPI RX FIFO, if there not empty read all the data avilable in the fifo and insert data to be transmited for the next SPI communicaiton
with the master , also 8 SPI words (16 bit ) , for test purpose the unit sends 8 words of 0xbb66 (this is validated on the master) side
this tested with various SPI CLK (2.5Mhz , 1Mhz ,400Khz) , and issue remain which is somtimes that data from the Slave look corrupted (as if it is shifted by few bits) it occur every 5 - 10 minutes
is there issue writting to SPI TX buffer on the slave side (assunming it is not full ) ? i am guessing there could some conflict when the slave writes to SPI TX FIFO while there is communication with SPI master
but i assume there should be any issue beacuse it write to FIFO and not directly to SPIDAT
please your advise on this matter