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TMS320F28027: SCI break cndition issue, strong related to power supply

Part Number: TMS320F28027

Hi expert,

My customer's project meet SCI communication failure, this failure is cased by SCI detected break condition.

Waveform:

Ch1: debug GPIO to indicate a break conditon happens

Ch2: debug GPIO to indicate sci receive ISR is entered

Ch3: Signal on SCI RX of F28027

They find below condition will make break condition LESS EASIER to happen:

1. Adding some lines in RX ISR

2. Lower the baud rate (typical 19200bps)

3. Same machine with same code programmed, but supplied with AC (the other way is supply with an adapter, in this case, break is completely removed when AC supplied)

4. Adding stop bit to two bits

5. Adding code in other part then a ISR, this issue will randomly appear or disappear. (Time of executing background loop may influence this issue)

Thanks

Sheldon

  • Sheldon,

    It is not clear why the changes you describe to the code code or power supply would affect the behavior of the SCI.  A break detect condition occurs when the SCIRXD is low for 9.625 bit periods following a missing stop bit.  (Note that the F2802x TRM shows 10 bit periods, but this has been corrected after the TRM was released).  At 19.2 kbps this would be approximately 500 microseconds and the oscilloscope screen capture confirms the trip since their signal is low for 517 microseconds.

    If the SCI becomes more stable due to the change in power supply as you described, then it might be a symptom of some other affect, such as the internal oscillator is increasing in frequency due to a higher input voltage.  Do you know the clock source?  If they are using the internal oscillator then its likely drifting due to voltage and they should be able to verify its accuracy.  Note that the accuracy can be improved with trimming.  See the TRM "Internal Oscillator Trim (INTOSCnTRIM) Register" on page 54.

    Also, for the SCI remember that with higher baud rates the error increases (see the TRM "SCI Baud Rate Calculations" section for more details).

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken

  • Hi Ken,

    Are there any support for "SCIRXD is low for 9.625 bit periods following a missing stop bit.", I can only find "SPRUI09–December 2018" on TI web site.

    Could you help me with updated material here?

    Thanks

    Sheldon

  • Hi Ken,

    In addition to that, since SCI state machine may wait for some bit time (SCIRXD is held low) then detect if stop bit comes or not.

    1. How long does it take to detect the stop bit? What will be the total time for this detection? (SCIRXD low + stop bit detection)

    2. How to detect the stop bit here? Rising edge, falling edge or majority vote or something?

    Thanks

    Sheldon

  • Sheldon,

    This update will be included in the next revision of the F2802x TRM.  The master file has already been updated for all TRMs.  You can see this update in the F2833x TRM SPRUI07 on page 591, as well as other TRM that have already been recently updated.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken

  • Sheldon,

    There are 8 SCICLK periods per data bit and the value for the data bit is based on using majority vote by making three samples in the middle of the bits.  These samples occur on the fourth, fifth, and sixth SCICLK periods, and bit-value determination is on a majority (two out of three) basis.  If after the stop bit the SCIRXD is low for 9.625 bit periods or a break detect condition will occur.

    Also, I created a new SCI block diagram which will be used in all updated and new TRMs and data sheets.  You can find it in the F2838x TRM (spruii0) on page 3536.  This is the first TRM to use the new block diagram.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken

  • Hi Ken,

    Very precise and good answer. Thanks a lot!

    Sheldon