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TMS320F28032: EPWM module generate a false pulse

Prodigy 50 points

Replies: 4

Views: 52

Part Number: TMS320F28032

Hi 

I am using EPWM1A of TMS320F28032 to control my single-ended inverter and I captured a false pulse during the operation.

The normal pulse width is about 5us and the false pulse width is about 53us.

I am using an up count for the counter. PWM output high when counter is zero and when counter equals to CMPA it will output low. The total PWM period is 66.7us(15kHz) but I am not using all the period time. I have a sync signal input to EPWM1 and when receive sync signal, counter will load phase shift value to finish the period earlier than 66.7us. Normal period is about 40us and pulse width is about 5us. The false pulse comes with width of 50us.

I found one note in the manual "NOTE: An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCTR count sequence. This can lead to a compare event being skipped. This skipping is considered normal operation and must be taken into account." I am suspecting it may be related to this but cannot confirm.

Can you please help to give some suggestion about my failure?

Below is my setting and control for EPWM1.

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //TB_SYNC_DISABLE

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm1Regs.AQSFRC.bit.RLDCSF = CC_CTR_ZERO;

EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD_10KHZ;

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;//TB_COUNT_UP; // Count up
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;//;ET_CTR_PRD; // Select INT on Period event
EPwm1Regs.ETSEL.bit.INTEN = 0; // Disenable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event

EPwm1Regs.ETCLR.bit.INT = 1;
/* Generate PWM */
EPwm1Regs.CMPA.half.CMPA = (EPwm1Regs.TBPRD*3>>5);
EPwm1Regs.CMPB = (EPwm1Regs.TBPRD>>2);

EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
u32delay = ((EPwm1Regs.TBPRD>>3));
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBPHS.half.TBPHS = u32delay;
EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;

EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;

EPwm1Regs.DBCTL.bit.HALFCYCLE = 0;
EPwm1Regs.DBCTL.bit.IN_MODE = DB_DISABLE;//DBA_RED_DBB_FED;
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;//DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBRED = 0;
EPwm1Regs.DBFED = 0;

/* for ADC trigger */
#if 1
EPwm1Regs.ETSEL.bit.SOCBEN = 1; // Enable SOC on B group
EPwm1Regs.ETSEL.bit.SOCBSEL = 6;//2; // Select SOC time-base counter equal to CMPB when the timer is incrementing
EPwm1Regs.ETPS.bit.SOCBCNT = 1; //1 event has occurred.
EPwm1Regs.ETPS.bit.SOCBPRD = 1; // Generate pulse on 1st event

#define SET_PWM_DUTY(X) {EPwm1Regs.TBPRD = GET_15K_PWM_PRD;\
EPwm1Regs.CMPA.half.CMPA = ((uint32)(Base_Time_10us * ((uint32)(X)) >>10));\
EPwm1Regs.CMPB = EPwm1Regs.CMPA.half.CMPA ; \
EPwm1Regs.TBPHS.half.TBPHS = ((uint32)(EPwm1Regs.TBPRD-(EPwm1Regs.TBPRD>>9) * Delay_Time));}

  • Fei,

    I would suggest monitoring the sync pulse and see if the "false pulse" always occurs after an external sync pulse.

    The problem you mentioned is reasonably common it depends on how your CMPx functions are set, the TBPHS value, and the value of your TBCTR when the sync pulse comes in.

    Please note that our PWMs use an "equal-to " compare module, if the TBCTR is counting up from 45, and CMPA is 43, the CMPA function will not take effect until TBCTR counts up to TBPRD and then resets and counts up to 43 again.

    Regards,
    Cody 

  • In reply to Cody Watkins:

    Thanks Cody. I monitored the sync signal and I found there is no abnormal for sync signal. For the false pulse, sync signal did not happen before CMPA value. So I am wondering what else can lead to missing CMPA compare. And I also found that in all the false pulse I captured, the pulse width is all around 53us.

    The period is 66.7us (15kHz) total count is 4000 at 60MHz, CMPA value is about 5us (~300 count), PHS value is 3608.

    From the current setting I cannot figure out why the false pulse width is always the same at about 53us. Do you have any comments on this?

    Thanks

    Fei 

  • In reply to Fei Shang:

    Fei,

    check to see if you are correctly using shadow loads for the CMPx registers. If you are changing the compare values on the fly it can lead to a missed compare event.

    Do you have anything setup in the digital compare or tripzone submodules? They have the ability to modify the PWM's output as well.

    Regards,
    Cody 

  • In reply to Cody Watkins:

    Fei,

    this thread will be closing soon due to inactivity. please let me know if you need more assistance.

    Regards,
    Cody

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