TMS320F28377D: Question about CLK and ADC characteristics data

Ryo Akashi

Genius 9470 points

Part Number: TMS320F28377D

Hello experts,

I got question about CLK, conversion rate and ADC characteristics from customer.

Could you give me advice?

1. about SYSCLK

In Table 5-12. Internal Clock Frequencies, SYSCLK range is 5-200MHz.

Is it possible to operate with over 200MHz?

For example, operate over 200MHz with using PLLRAWCLK(120~400MHz) in Figure 5-7 Clocking System.

2. about ADCCLK

From ADCCLK PRESCALE setting, we can set ADCCLK same level as SYSCLK.

If we operate ADCCLK over 50MHz, what point should we take care?

By using fast CLK, customer want to make ADC conversion speed faster.

3.about sampling rate

In datasheet P1 Analog subsystem, there is description "(up to 4.4-MSPS system throughput)" @ 16-bit mode.

Could you tell us the calculation of this?

4. about ADC characteristic graph

Do you have detailed characteristic graph data (especially, SNR) like attached file?

AnalogDevices_0900766b80e42f7f.pdf

I would appreciate if you would give me reply.

Thanks and best regards,

Ryo Akashi

over 5 years ago

0 Devin Cottier over 5 years ago

TI__Guru 60865 points

Hi Akashi-san,

1 & 2) No, it is not possible to reliably operate the device or ADC beyond the recommended operating range.

3) Each ADC is 1.1MSPS so the system can throughput 1.1MSPS x 4 = 4.4MSPS in 16-bit mode since there are 4 ADC modules that can sample 4 signals in parallel. To determine the sample rate on a single ADC, refer to the ADC timing section of the datasheet

For example, with the minimum S+H time of 320ns (64 SYSCLKs), the total time between conversions if SYSCLK is 200MHz, PRESCALE = /4, ADCCLK = 50MHz would be:

Tsh + Teoc = 64 SYSCLKs + 119 SYSCLKs = 183 SYSCLKs or 183 SYSCLKs * 5ns = 915ns

1/915ns = 1.1MHz

Fig. 12: For SNR, we would also expect F2837x ADC to have 6dB of increase in SNR for a doubling of the reference range. SNR is specified on F2837x with the min. VREF of 2.5V, so going to the maximum VREF of about 3.3V would gain roughly 20*log(3.3/2.5) = 2.4 dB

Fig. 14: SNR for 16-bit ADC on F2837x is specified with 10kHz input. Our SNR vs. frequency will be have a pretty similar characteristic; roughly 20dB/decade roll-off in SNR at some point past 10kHz (I believe the knee is at about 20kHz). This is due to aperture jitter effects.

0 Ryo Akashi over 5 years ago in reply to Devin Cottier

TI__Genius 9470 points

Hello Devin-san,

Thank you for your reply.

I understand the details.

Regrading question 4), let me ask question.

Do you have any graph or detailed data for SNR and SINAD which you mentioned?

Also, if you have temperature drift data, could you share me?

Thanks and best regards,

Ryo Akashi

0 Devin Cottier over 5 years ago in reply to Ryo Akashi

TI__Guru 60865 points

Hi Akashi-san,

Attached is a some typical data for SINAD vs Fin for 16B differential mode across temperature for some F2838x devices. F2838x has the same ADC as F2837x.

I don't have any handy graphical data for ADC performance across VREF voltages, but the data in the DS is with VREFHI = 2.5V, which should be worst-case.