Hello,
we use the EPWM outputs of the TMS320F28069 as control for a half bridge.
After initialisation, only the compare value of the PWM machine is adjusted.
This takes place in the CLA interrupt. The PWM machine is operated in UpDown-Mode at 30kHz.
Epwm1A and Epwm1B are used for upper and lower IGBT synchronously and inverted.
We want to change the dutycycle at CTR = Zero and CTR = Period. CMPA shall be used for both PWMs.
In my tests I noticed that 2 to 3 times the CLA_int is entered before the Compare-Value is effective.
My expectation would be that a Comparevalue which is calculated in CLA_int will be effective from the next CTR = Zero or CTR = Period Event.
Where can this delay come from?
Epwm1 is initialized like this:
EPwm1Regs.TBPRD = PWM_PERIODE_USED; //90e6/30e3
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_CLKDIV_DIV1; //0
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_HSPCLKDIV_DIV1; //0
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //1
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; //0
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; //0
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; //2
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //0
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; //0
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; //2
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; //2
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; //1
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; //2
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; //2 - probably not needed
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR; //1 - probably not needed
EPwm1Regs.DBCTL.bit.HALFCYCLE = 0;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; //0
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; //2
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //3
EPwm1Regs.DBRED = 42;
EPwm1Regs.DBFED = 42;
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0;
Regards,
Dominik