Compiler/TMS320F280049: #17003-D Warning while include Resolver_Lib_CLA_Float.lib

Benjamin Zhou

Part Number: TMS320F280049

Tool/software: TI C/C++ Compiler

Hi Team,

My customer used F280049 CLA software resolver library Resolver_Lib_CLA_Float.lib, and reported an "#17003-D Warning", while removed the Resolver_Lib_CLA_Float.lib file, this warning removed; also has enlarger the size of CLA_scratchpad_SIZE and not removed the file， the warning still existed;

Description Resource Path Location Type

<a href="processors.wiki.ti.com/.../17003"> relocation to symbol "CLAscratch_end" overflowed; the 5-bit relocated address 0xf6 is too large to encode in the 16-bit unsigned field (type = 'R_ABS16_OC' (107), file = "../12_CLA/lib/Resolver_Lib_CLA_float.lib<Resolver_CLA_Source.obj>", offset = 0x00000326, section = "Cla1Prog") SD100_7300 C/C++ Problem

could you kindly give comments on how to remove the warning? Expect for your reply, thanks.

Best Regards

Benjamin

over 3 years ago

0 Lori Heustess over 3 years ago

TI__Guru* 89465 points

Benjamin,

What does the user's linker command file look like for the CLA sections? I would double check that they are using valid memory for the CLA as a first step.

Regards

Lori

0 Benjamin Zhou over 3 years ago in reply to Lori Heustess

TI__Expert 4000 points

Hi lori,

Attached is the CMD file, could you kindly double check it? Expect for your reply, thanks.

8546.cmd.txt

// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN            : origin = 0x080000, length = 0x000002
   RAMM0            : origin = 0x0000F3, length = 0x00030D

   RAMLS0           : origin = 0x008000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
   RAMLS4           : origin = 0x00A000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002

/* Flash sectors */
   /* BANK 0 */
   FLASH_BANK0_SEC0  : origin = 0x080002, length = 0x000FFE	/* on-chip Flash */
   FLASH_BANK0_SEC1  : origin = 0x081000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC2  : origin = 0x082000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC3  : origin = 0x083000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC4  : origin = 0x084000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC5  : origin = 0x085000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC6  : origin = 0x086000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC7  : origin = 0x087000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC8  : origin = 0x088000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC9  : origin = 0x089000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x00F80	/* on-chip Flash */
   CSM_RSVD          : origin = 0x08FF82, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   CSM_PWL_P0        : origin = 0x08FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   /* BANK 1 */
   FLASH_BANK1_SEC0  : origin = 0x090000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC1  : origin = 0x091000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC2  : origin = 0x092000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC3  : origin = 0x093000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC4  : origin = 0x094000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC5  : origin = 0x095000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC6  : origin = 0x096000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC7  : origin = 0x097000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC8  : origin = 0x098000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC9  : origin = 0x099000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0	/* on-chip Flash */

   FPUTABLES         : origin = 0x3F9200, length = 0x001800	    /* FPU Tables in Boot ROM */

//   IQTABLES          : origin = 0x3F0800, length = 0x000F00     /* IQ Math Tables in Boot ROM */
//   IQTABLES2         : origin = 0x3F1700, length = 0x000100     /* IQ Math Tables in Boot ROM */
//   IQTABLES3         : origin = 0x3F1800, length = 0x000100	    /* IQ Math Tables in Boot ROM */

   ROM               : origin = 0x3FEB22, length = 0x000B13     /* Boot ROM */
   VECTORS           : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x0000F1     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800

   RAMGS0           : origin = 0x00C000, length = 0x002000
   RAMGS1           : origin = 0x00E000, length = 0x002000
   RAMGS2           : origin = 0x010000, length = 0x002000
   RAMGS3           : origin = 0x012000, length = 0x001FF8
//   RAMGS3_RSVD      : origin = 0x013FF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   CLA1_MSGRAMLOW   : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500, length = 0x000080

//   CLA_CPU_MSGRAM  : origin = 0x001480, length = 0x000080 /* CLA-R/W, CPU-R message RAM */
//   CPU_CLA_MSGRAM  : origin = 0x001500, length = 0x000080 /* CPU-R/W, CLA-R message RAM */

}


SECTIONS
{
   .cinit           : > FLASH_BANK0_SEC0,     PAGE = 0, ALIGN(4)
   .text            : >>FLASH_BANK0_SEC1 | FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC4 | FLASH_BANK0_SEC5 | FLASH_BANK0_SEC6
   | FLASH_BANK0_SEC7 | FLASH_BANK0_SEC8 | FLASH_BANK0_SEC9 | FLASH_BANK0_SEC10 | FLASH_BANK0_SEC11 | FLASH_BANK0_SEC12  ,   PAGE = 0, ALIGN(4)
   codestart        : > BEGIN       PAGE = 0, ALIGN(4)

   .stack           : > RAMM1        PAGE = 1
   .switch          : > FLASH_BANK0_SEC0,     PAGE = 0, ALIGN(4)

#if defined(__TI_EABI__)
   .init_array      : > FLASH_BANK0_SEC0,       PAGE = 0,       ALIGN(4)
   .bss             : > RAMLS5,       PAGE = 1
   .bss:output      : > RAMLS5,       PAGE = 1
   .bss:cio         : > RAMLS5,       PAGE = 1
   .data            : > RAMLS6,       PAGE = 1
   .sysmem          : > RAMLS6,       PAGE = 1
   .const           : >> FLASH_BANK0_SEC14 | FLASH_BANK0_SEC15,       PAGE = 0,       ALIGN(4)
#else
   .pinit           : > FLASH_BANK0_SEC0,       PAGE = 0,       ALIGN(4)
   .ebss            : >>RAMLS5 | RAMLS6 | RAMLS7 | RAMGS0 ,       PAGE = 1
   .esysmem         : > RAMLS6,       PAGE = 1
   .cio             : > RAMLS5,       PAGE = 1
   .econst          : >>FLASH_BANK0_SEC14 | FLASH_BANK0_SEC15,    PAGE = 0, ALIGN(4)
#endif

   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1

   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   csmpasswds       : > CSM_PWL_P0, PAGE = 0
   csm_rsvd         : > CSM_RSVD,   PAGE = 0

   /* Allocate IQ math areas: */
//   IQmath           : > FLASH_BANK0_SEC13,    PAGE = 0            /* Math Code */
//   IQmathTables     : > IQTABLES,       PAGE = 0, TYPE = NOLOAD
   /* Allocate IQ math areas: */
   IQmath			: > FLASH_BANK1_SEC2, PAGE = 0, ALIGN(8)            /* Math Code */
   IQmathTables		: > FLASH_BANK1_SEC3, PAGE = 0, ALIGN(8)
   /* Allocate FPU math areas: */
   FPUmathTables    : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD

   debug_buffer     : > RAMGS3,      PAGE = 1

   vectors          : > VECTORS,    PAGE = 0, TYPE = DSECT

#if defined(__TI_EABI__)
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK1_SEC0,
                      RUN = RAMLS0,
                      LOAD_START(Cla1ProgLoadStart),
                      RUN_START(Cla1ProgRunStart),
                      LOAD_SIZE(Cla1ProgLoadSize),
                      PAGE = 0, ALIGN(4)
#else
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK1_SEC0,
                      RUN = RAMLS0,
                      LOAD_START(_Cla1ProgLoadStart),
                      RUN_START(_Cla1ProgRunStart),
                      LOAD_SIZE(_Cla1ProgLoadSize),
                      PAGE = 0, ALIGN(4)
#endif

    Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
    CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1

#if defined(__TI_EABI__)
   .TI.ramfunc      : LOAD = FLASH_BANK0_SEC0,
                      RUN = RAMLS4
                      LOAD_START(RamfuncsLoadStart),
                      LOAD_SIZE(RamfuncsLoadSize),
                      LOAD_END(RamfuncsLoadEnd),
                      RUN_START(RamfuncsRunStart),
                      RUN_SIZE(RamfuncsRunSize),
                      RUN_END(RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)
#else
   .TI.ramfunc      : LOAD = FLASH_BANK0_SEC0,
                      RUN = RAMLS4
                      LOAD_START(_RamfuncsLoadStart),
                      LOAD_SIZE(_RamfuncsLoadSize),
                      LOAD_END(_RamfuncsLoadEnd),
                      RUN_START(_RamfuncsRunStart),
                      RUN_SIZE(_RamfuncsRunSize),
                      RUN_END(_RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)
#endif
   .scratchpad       : >> RAMGS1 | RAMGS2 | RAMGS3 ,   PAGE = 1
//   .scratchpad      : > RAMGS1,           PAGE = 1
   .bss_cla         : > RAMLS1,           PAGE = 1

   Cla1DataRam      : > RAMLS2,           PAGE = 1
   cla_shared       : > RAMLS1,           PAGE = 1

   CLAmathTables	: > RAMLS1,		      PAGE = 1
   CLA1mathTables	: > RAMLS1,		      PAGE = 1

#if defined(__TI_EABI__)
   .const_cla      : LOAD = FLASH_BANK1_SEC2,
                      RUN = RAMLS3,
                      RUN_START(Cla1ConstRunStart),
                      LOAD_START(Cla1ConstLoadStart),
                      LOAD_SIZE(Cla1ConstLoadSize),
                      PAGE = 0, ALIGN(4)
#else
   .const_cla      : LOAD = FLASH_BANK1_SEC2,
                      RUN = RAMLS3,
                      RUN_START(_Cla1ConstRunStart),
                      LOAD_START(_Cla1ConstLoadStart),
                      LOAD_SIZE(_Cla1ConstLoadSize),
                      PAGE = 0, ALIGN(4)
#endif

   CLAscratch       :
                        { *.obj(CLAscratch)
                        . += CLA_SCRATCHPAD_SIZE;
                        *.obj(CLAscratch_end) } >  RAMGS3,  PAGE = 1, ALIGN=2
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Best Regards

Benjamin

0 Lori Heustess over 3 years ago in reply to Benjamin Zhou

TI__Guru* 89465 points

Benjamin,

The CLA's .scratchpad is allocated to GSx memory which is not accessible by the CLA. Refer to the memory map in the device data sheet.

Regards

Lori

0 Chen Yang over 3 years ago in reply to Lori Heustess

TI__Intellectual 2720 points

Hi Lori,

I have the same customer with Benjamin, I told customer what you advised, and customer revised cmd twice as attach files, but the problem still unsolved.

Could you please double check it?

Thank you so much!

cmd (2).txt

CLA_SCRATCHPAD_SIZE = 0x200;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN            : origin = 0x080000, length = 0x000002
   RAMM0            : origin = 0x0000F3, length = 0x00030D

   RAMLS0           : origin = 0x008000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
   RAMLS4           : origin = 0x00A000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002

/* Flash sectors */
   /* BANK 0 */
   FLASH_BANK0_SEC0  : origin = 0x080002, length = 0x000FFE	/* on-chip Flash */
   FLASH_BANK0_SEC1  : origin = 0x081000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC2  : origin = 0x082000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC3  : origin = 0x083000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC4  : origin = 0x084000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC5  : origin = 0x085000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC6  : origin = 0x086000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC7  : origin = 0x087000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC8  : origin = 0x088000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC9  : origin = 0x089000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x00F80	/* on-chip Flash */
   CSM_RSVD          : origin = 0x08FF82, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   CSM_PWL_P0        : origin = 0x08FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   /* BANK 1 */
   FLASH_BANK1_SEC0  : origin = 0x090000, length = 0x004000	/* on-chip Flash */
   FLASH_BANK1_SEC1  : origin = 0x094000, length = 0x004000	/* on-chip Flash */
   FLASH_BANK1_SEC2  : origin = 0x098000, length = 0x004000	/* on-chip Flash */
   FLASH_BANK1_SEC3  : origin = 0x09C000, length = 0x002000	/* on-chip Flash */
   FLASH_BANK1_SEC4 : origin = 0x09E000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC5 : origin = 0x09F000, length = 0x000FF0	/* on-chip Flash */

   FPUTABLES         : origin = 0x3F9200, length = 0x001800	    /* FPU Tables in Boot ROM */

//   IQTABLES          : origin = 0x3F0800, length = 0x000F00     /* IQ Math Tables in Boot ROM */
//   IQTABLES2         : origin = 0x3F1700, length = 0x000100     /* IQ Math Tables in Boot ROM */
//   IQTABLES3         : origin = 0x3F1800, length = 0x000100	    /* IQ Math Tables in Boot ROM */

   ROM               : origin = 0x3FEB22, length = 0x000B13     /* Boot ROM */
   VECTORS           : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x0000F1     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800

   RAMGS0           : origin = 0x00C000, length = 0x002000
   RAMGS1           : origin = 0x00E000, length = 0x002000
   RAMGS2           : origin = 0x010000, length = 0x002000
   RAMGS3           : origin = 0x012000, length = 0x001FF8
//   RAMGS3_RSVD      : origin = 0x013FF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   CLA1_MSGRAMLOW   : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500, length = 0x000080

}


SECTIONS
{
   .cinit           : > FLASH_BANK0_SEC0,     PAGE = 0, ALIGN(4)
   .text            : >>FLASH_BANK0_SEC1 | FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC4 | FLASH_BANK0_SEC5 | FLASH_BANK0_SEC6
   | FLASH_BANK0_SEC7 | FLASH_BANK0_SEC8 | FLASH_BANK0_SEC9 | FLASH_BANK0_SEC10 | FLASH_BANK0_SEC11 | FLASH_BANK0_SEC12  ,   PAGE = 0, ALIGN(4)
   codestart        : > BEGIN       PAGE = 0, ALIGN(4)

   .stack           : > RAMM1        PAGE = 1
   .switch          : > FLASH_BANK0_SEC0,     PAGE = 0, ALIGN(4)

#if defined(__TI_EABI__)
   .init_array      : > FLASH_BANK0_SEC0,       PAGE = 0,       ALIGN(4)
   .bss             : > RAMLS5,       PAGE = 1
   .bss:output      : > RAMLS5,       PAGE = 1
   .bss:cio         : > RAMLS5,       PAGE = 1
   .data            : > RAMLS6,       PAGE = 1
   .sysmem          : > RAMLS6,       PAGE = 1
   .const           : >> FLASH_BANK0_SEC14 | FLASH_BANK0_SEC15,       PAGE = 0,       ALIGN(4)
#else
   .pinit           : > FLASH_BANK0_SEC0,       PAGE = 0,       ALIGN(4)
   .ebss            : >>RAMLS5 | RAMLS6 | RAMLS7 | RAMGS0 ,       PAGE = 1
   .esysmem         : > RAMLS6,       PAGE = 1
   .cio             : > RAMLS5,       PAGE = 1
   .econst          : >>FLASH_BANK0_SEC14 | FLASH_BANK0_SEC15,    PAGE = 0, ALIGN(4)
#endif

   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1

   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   csmpasswds       : > CSM_PWL_P0, PAGE = 0
   csm_rsvd         : > CSM_RSVD,   PAGE = 0

   /* Allocate IQ math areas: */
//   IQmath           : > FLASH_BANK0_SEC13,    PAGE = 0            /* Math Code */
//   IQmathTables     : > IQTABLES,       PAGE = 0, TYPE = NOLOAD
   /* Allocate IQ math areas: */
   IQmath			: > FLASH_BANK1_SEC2, PAGE = 0, ALIGN(8)            /* Math Code */
   IQmathTables		: > FLASH_BANK1_SEC3, PAGE = 0, ALIGN(8)
   /* Allocate FPU math areas: */
   FPUmathTables    : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD

   debug_buffer     : > RAMGS3,      PAGE = 1

   vectors          : > VECTORS,    PAGE = 0, TYPE = DSECT

#if defined(__TI_EABI__)
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK1_SEC0,
                      RUN = RAMLS0,
                      LOAD_START(Cla1ProgLoadStart),
                      RUN_START(Cla1ProgRunStart),
                      LOAD_SIZE(Cla1ProgLoadSize),
                      PAGE = 0, ALIGN(4)
#else
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK1_SEC0,
                      RUN = RAMLS0,
                      LOAD_START(_Cla1ProgLoadStart),
                      RUN_START(_Cla1ProgRunStart),
                      LOAD_SIZE(_Cla1ProgLoadSize),
                      PAGE = 0, ALIGN(4)
#endif


    Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
    CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1

#if defined(__TI_EABI__)
   .TI.ramfunc      : LOAD = FLASH_BANK0_SEC0,
                      RUN = RAMLS4
                      LOAD_START(RamfuncsLoadStart),
                      LOAD_SIZE(RamfuncsLoadSize),
                      LOAD_END(RamfuncsLoadEnd),
                      RUN_START(RamfuncsRunStart),
                      RUN_SIZE(RamfuncsRunSize),
                      RUN_END(RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)
#else
   .TI.ramfunc      : LOAD = FLASH_BANK0_SEC0,
                      RUN = RAMLS4
                      LOAD_START(_RamfuncsLoadStart),
                      LOAD_SIZE(_RamfuncsLoadSize),
                      LOAD_END(_RamfuncsLoadEnd),
                      RUN_START(_RamfuncsRunStart),
                      RUN_SIZE(_RamfuncsRunSize),
                      RUN_END(_RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)
#endif

   .scratchpad      : > RAMLS0,           PAGE = 0
   .bss_cla         : > RAMLS1,           PAGE = 1

   Cla1DataRam      : > RAMLS2,           PAGE = 1
   cla_shared       : > RAMLS1,           PAGE = 1

   CLAmathTables	: > RAMLS1,		      PAGE = 1
   CLA1mathTables	: > RAMLS1,		      PAGE = 1

#if defined(__TI_EABI__)
   .const_cla      : LOAD = FLASH_BANK1_SEC1,
                      RUN = RAMLS3,
                      RUN_START(Cla1ConstRunStart),
                      LOAD_START(Cla1ConstLoadStart),
                      LOAD_SIZE(Cla1ConstLoadSize),
                      PAGE = 0, ALIGN(4)
#else
   .const_cla      : LOAD = FLASH_BANK1_SEC1,
                      RUN = RAMLS3,
                      RUN_START(_Cla1ConstRunStart),
                      LOAD_START(_Cla1ConstLoadStart),
                      LOAD_SIZE(_Cla1ConstLoadSize),
                      PAGE = 0, ALIGN(4)
#endif

   CLAscratch       :
                        { *.obj(CLAscratch)
                        . += CLA_SCRATCHPAD_SIZE;
                        *.obj(CLAscratch_end) } >  RAMGS1,  PAGE = 1, ALIGN=2
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

5531.28004x_cla_flash_lnk.txt

CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN            : origin = 0x080000, length = 0x000002
   RAMM0            : origin = 0x0000F3, length = 0x00030D

   RAMLS0           : origin = 0x008000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
   RAMLS4           : origin = 0x00A000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002

/* Flash sectors */
   /* BANK 0 */
   FLASH_BANK0_SEC0  : origin = 0x080002, length = 0x000FFE	/* on-chip Flash */
   FLASH_BANK0_SEC1  : origin = 0x081000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC2  : origin = 0x082000, length = 0x004000	/* on-chip Flash */
   FLASH_BANK0_SEC3  : origin = 0x086000, length = 0x004000	/* on-chip Flash */
   FLASH_BANK0_SEC4  : origin = 0x08A000, length = 0x004000	/* on-chip Flash */
   FLASH_BANK0_SEC5  : origin = 0x08E000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC6  : origin = 0x08F000, length = 0x00F80	/* on-chip Flash */
   CSM_RSVD          : origin = 0x08FF82, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   CSM_PWL_P0        : origin = 0x08FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   /* BANK 1 */
   FLASH_BANK1_SEC0  : origin = 0x090000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC1  : origin = 0x091000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC2  : origin = 0x092000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC3  : origin = 0x093000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC4  : origin = 0x094000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC5  : origin = 0x095000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC6  : origin = 0x096000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC7  : origin = 0x097000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC8  : origin = 0x098000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC9  : origin = 0x099000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0	/* on-chip Flash */

   FPUTABLES         : origin = 0x3F9200, length = 0x001800	    /* FPU Tables in Boot ROM */
//   FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010  /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x0000F1     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800

   RAMGS0           : origin = 0x00C000, length = 0x002000
   RAMGS1           : origin = 0x00E000, length = 0x002000
   RAMGS2           : origin = 0x010000, length = 0x002000
   RAMGS3           : origin = 0x012000, length = 0x001FF8
//   RAMGS3_RSVD      : origin = 0x013FF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   CLA1_MSGRAMLOW   : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500, length = 0x000080
}


SECTIONS
{
   .cinit           : > FLASH_BANK0_SEC1,     PAGE = 0, ALIGN(4)
   .text            : >>FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC4 ,   PAGE = 0, ALIGN(4)
   codestart        : > BEGIN       PAGE = 0, ALIGN(4)
   
   .stack           : > RAMM1        PAGE = 1
   .switch          : > FLASH_BANK0_SEC1,     PAGE = 0, ALIGN(4)

#if defined(__TI_EABI__)
   .init_array      : > FLASH_BANK0_SEC1,       PAGE = 0,       ALIGN(4)
   .bss             : > RAMLS5,       PAGE = 1
   .bss:output      : > RAMLS5,       PAGE = 1
   .bss:cio         : > RAMLS5,       PAGE = 1
   .data            : > RAMLS6,       PAGE = 1
   .sysmem          : > RAMLS6,       PAGE = 1
   .const           : > FLASH_BANK0_SEC4,       PAGE = 0,       ALIGN(4)
#else
   .pinit           : > FLASH_BANK0_SEC1,       PAGE = 0,       ALIGN(4)
   .ebss            : >>RAMLS5 | RAMLS6 | RAMLS7 |  RAMGS0  ,       PAGE = 1
   .esysmem         : > RAMLS6,       PAGE = 1
   .cio             : > RAMLS5,       PAGE = 1
   .econst          : > FLASH_BANK0_SEC4,    PAGE = 0, ALIGN(4)
#endif

   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1
    
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
   
   csmpasswds       : > CSM_PWL_P0, PAGE = 0
   csm_rsvd         : > CSM_RSVD,   PAGE = 0

   /* Allocate IQ math areas: */
   IQmath			: > FLASH_BANK0_SEC6, PAGE = 0, ALIGN(8)            /* Math Code */
   IQmathTables		: > FLASH_BANK0_SEC6, PAGE = 0, ALIGN(8)
   /* Allocate FPU math areas: */
   FPUmathTables    : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD

#if defined(__TI_EABI__)
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK0_SEC4,
                      RUN = RAMLS0,
                      LOAD_START(Cla1ProgLoadStart),
                      RUN_START(Cla1ProgRunStart),
                      LOAD_SIZE(Cla1ProgLoadSize),
                      PAGE = 0, ALIGN(4)
#else
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK0_SEC4,
                      RUN = RAMLS0,
                      LOAD_START(_Cla1ProgLoadStart),
                      RUN_START(_Cla1ProgRunStart),
                      LOAD_SIZE(_Cla1ProgLoadSize),
                      PAGE = 0, ALIGN(4)
#endif
  
    
    Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
    CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1

#if defined(__TI_EABI__)
   .TI.ramfunc      : LOAD = FLASH_BANK0_SEC1,
                      RUN = RAMLS4
                      LOAD_START(RamfuncsLoadStart),
                      LOAD_SIZE(RamfuncsLoadSize),
                      LOAD_END(RamfuncsLoadEnd),
                      RUN_START(RamfuncsRunStart),
                      RUN_SIZE(RamfuncsRunSize),
                      RUN_END(RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)
#else
   .TI.ramfunc      : LOAD = FLASH_BANK0_SEC1,
                      RUN = RAMLS4
                      LOAD_START(_RamfuncsLoadStart),
                      LOAD_SIZE(_RamfuncsLoadSize),
                      LOAD_END(_RamfuncsLoadEnd),
                      RUN_START(_RamfuncsRunStart),
                      RUN_SIZE(_RamfuncsRunSize),
                      RUN_END(_RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)
#endif
   .scratchpad      : > RAMLS1,           PAGE = 1
   .bss_cla         : > RAMLS1,           PAGE = 1

   Cla1DataRam      : > RAMLS2,           PAGE = 1
   cla_shared       : > RAMLS1,           PAGE = 1
#if defined(__TI_EABI__)
   .const_cla      : LOAD = FLASH_BANK0_SEC2,
                      RUN = RAMLS3,
                      RUN_START(Cla1ConstRunStart),
                      LOAD_START(Cla1ConstLoadStart),
                      LOAD_SIZE(Cla1ConstLoadSize),
                      PAGE = 0, ALIGN(4)
#else
   .const_cla      : LOAD = FLASH_BANK0_SEC2,
                      RUN = RAMLS3,
                      RUN_START(_Cla1ConstRunStart),
                      LOAD_START(_Cla1ConstLoadStart),
                      LOAD_SIZE(_Cla1ConstLoadSize),
                      PAGE = 0, ALIGN(4)
#endif

   CLAscratch       :
                        { *.obj(CLAscratch)
                        . += CLA_SCRATCHPAD_SIZE;
                        *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 1, ALIGN=2
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 Lori Heustess over 3 years ago in reply to Chen Yang

TI__Guru* 89465 points

Chen,

Did the error message change at all? Please provide the whole error or a screenshot of the error. Which compiler version are they using and are they compiling for EABI?

Regards

Lori

0 Lori Heustess over 3 years ago in reply to Lori Heustess

TI__Guru* 89465 points

Chen,

Also please send the .map file.

Regards

Lori

0 Chen Yang over 3 years ago in reply to Lori Heustess

TI__Intellectual 2720 points

Lori,

Thanks so much for your help.

The files as your advices are attached.

warnings & .map.7z

Looking forward for your reply.

Chen

0 Lori Heustess over 3 years ago in reply to Chen Yang

TI__Guru* 89465 points

Thank you Chen. I am consulting with members of the compiler team and will get back to you.

0 GregM over 3 years ago in reply to Lori Heustess

TI__Expert 4745 points

Chen,

I cannot reproduce their issue. I see their map file includes __cla_scratchpad_end/start. Do you know what they are using those symbols for in their application?

For CLA type 2, the only linker cmd file entry needed for CLA scratch should be below:

.scratchpad : > RAMLS1, PAGE = 1

So if they are not actually using __cla_scratchpad_end/start, then have them remove below entries from their linker cmd file:

CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start

CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 1, ALIGN=2

Thanks,

Greg

0 Chen Yang over 3 years ago in reply to Lori Heustess

TI__Intellectual 2720 points

Lori,

Thank you so much.

Looking for your reply.

0 Chen Yang over 3 years ago in reply to GregM

TI__Intellectual 2720 points

Hi GregM,

Thanks for your kindly help.

i met the same problems with customer with the same work, porting TMDSRSLVR_v1.0/F28035_CLA to F280049_CLA, including Resolver_CLA_float.lib and Reslover_CLA.h.

customers remove the parts:

CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start

CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 1, ALIGN=2

But the warnings still exist.

I attach my project files for clear understanding of this issue.

Thank you so mcuh!

1348.project.rar

0 GregM over 3 years ago in reply to Chen Yang

TI__Expert 4745 points

Chen,

Can you please send details on how to reproduce the issue?

Thanks
Greg

0 Chen Yang over 3 years ago in reply to GregM

TI__Intellectual 2720 points

Hi Lori & Greg,

I have no error before on ccs and f280049, and I finished porting TMDSRSLVR_resolver project f28035 to f280049 based on C28, and it works.

But, when I try to porting f28035_CLA project to f280049, the issue occurred. And next is my steps.

First, I just init the modules like ADC, epwm, DAC(instead of epwm to generate EXC sin signal, I use DAC to output sin signal) and init_CLA as the attach file shows;

Second, configure epwm_CMPA_Int & ISR(postprocess_ISR) and ADC_INT & ISR(resolver_algo_CLA defined in Resolver_Lib_CLA_float.lib) in CLA task2, CLA task1 used to call function init_resolver_CLA (defined in Resolver_Lib_CLA_float.lib).

Finally, the warning occurred after build, with no error just a series of #17003-D warings as same as customer.

And, could you please take a webex meeting with Benjamin and me? we have to solve this urgent problem!

Thank you so much.

0 Chen Yang over 3 years ago in reply to GregM

TI__Intellectual 2720 points

Hi Greg,

Thanks so much for your time and patient help.

it a __cla_scratchpad_end/start problem, as your advice i revised below codes to cmd, and the #17003-D warnings are removed.

// GREG: added below from F28035_FLASH_Resolver.CMD
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start


// GREG: added below also from F28035_FLASH_Resolver.CMD
//       and changed from >RAML2 to >RAMLS1
  CLAscratch       :
                     { *.lib(CLAscratch)
                      . += CLA_SCRATCHPAD_SIZE;
                      *.lib(CLAscratch_end) } > RAMLS1,  /* RAML2,*/
                      PAGE = 1

thank you so much again.

C2000™︎ microcontrollers

C2000 microcontrollers forum

Compiler/TMS320F280049: #17003-D Warning while include Resolver_Lib_CLA_Float.lib