TMS320F28379D: Two memories on EMIF1 (One of them not working after while) [Flash/Mram]

Marek,

Contention between memory components would be unusual because the EMIF provides arbitration of the CS/CE signals.

One oddity that I am aware of is that the Flash RY/BY# signal takes a considerable amount of time (in EMIF terms) to become valid -- so the EMIF Extended Wait functionality may not work correctly if you configure the timings based on non-program operations. The flash example in C2000Ware handles this by polling on the RY/BY# signal using GPIO: ~\C2000Ware_XXXX\device_support\f2837xd\examples\cpu1\emif_dc_flash

Are you able to determine which signal(s) might be damaged on the MRAM?  This might help to identify the cause.  It might be a good idea to scope the CS signals to make sure that they are reaching the expected voltage levels without overlap.

Some minor observations from the schematics:

• The GPIO72 switch is probably not  necessary -- a weak boot-strap pull resistor is not expected to degrade the EMIF functionality
• EMIF1An functions can be used instead of EMIF1DQn for 16-b memories -- the UB/LB signals can be pulled down permanently because the C28x will always perform 16-b accesses
• A17 is skipped on the MRAM

-Tommy

Hello, thanks for fast reply. For Flash writing Im using EMIF_DC_programCS2Flash, but what I forgot to set up are these three variables:
Should I set to the GPIO number or physical pin number on the processor? Could this be the cause? Because fuctionCS2Flash wait till EMIF_DC_FLASH_READY == 1 but its not for now...



EDIT: (NVM, FLASH_READY pin is 36 like in photo, same for others...)

For sector erase (chip erase).. Im using S29GLxxxS library, Erase will be performed when data need to be writen on new page of Flash, but when program start sector erase, and i got IPC to MRAM write and read can't it go crazy during this cycle?



For MRAM, Im try only GPIO method with EMIF off, so I induced Word Read and Word Write states (in MRAM datasheet) only with gpio  turn on/off, Im wanted to write 1 0 1 0 1 0 .. sequence, but when i read it back i got only 0 0 0 0 0 0 on all EM1Dn pins (like in memory browser in CCS). So i dont really know what a specific pin was damaged.

• When I didn't have this GPIO72 switch i cannot boot from standalone mode
• Yes you are right, UB/LB can be pulled down
• I know about that A17 is not connected (will be corrected in a new revision), but i hope that cannot cause this issue
  
  

I dont know if it help, but this is my MRAM and FLASH settings (emif on 100 MHz):
MRAM


FLASH

Marek Oravec said:

For sector erase (chip erase).. Im using S29GLxxxS library, Erase will be performed when data need to be writen on new page of Flash, but when program start sector erase, and i got IPC to MRAM write and read can't it go crazy during this cycle?

Yes, for special flash instructions that require additional wait cycles, you would want to hold-off MRAM accesses until the flash operation completes.

Marek Oravec said:

For MRAM, Im try only GPIO method with EMIF off, so I induced Word Read and Word Write states (in MRAM datasheet) only with gpio  turn on/off, Im wanted to write 1 0 1 0 1 0 .. sequence, but when i read it back i got only 0 0 0 0 0 0 on all EM1Dn pins (like in memory browser in CCS). So i dont really know what a specific pin was damaged.

Can you check the voltage levels on the MRAM signal pins while progressing through the read and write sequences?

Marek Oravec said:

When I didn't have this GPIO72 switch i cannot boot from standalone mode

It's ok to keep the switch, but if you were not able to boot with the pull resistor, it points to some potential contention at power up.  For example, the GPIO pins act as inputs during reset so the memory control signals are not biased by the F2837x during this time. It's possible that the memories may find themselves in an unintended read state where they drive output on the data bus.  This can be mitigated by installing pull-up resistors on the CS signals so that the devices will revert to a de-selected state when the CS signal is not actively controlled.

Marek Oravec said:

I dont know if it help, but this is my MRAM and FLASH settings (emif on 100 MHz)

Nothing stands out to me as being problematic.  You can also use the EMIF configuration tool in C2000Ware to double-check your settings: ~\C2000Ware_XXXX\boards\TIDesigns\F28379D_EMIF_DC\C2000-EMIF_ConfigurationTool.xlsx

There is also some usage information in this EMIF appnote.

Hello, I added some wait states when the flash chip/sector erasing. I added wait state also before MRAM write cycle. I hope it helps.

#define FlashReadyStatus (GpioDataRegs.GPBDAT.bit.GPIO36) // Ready/Busy (Ready - 1 | Busy - 0)

void lld_SectorEraseCmd
(
FLASHDATA * base_addr,                   /* device base address in system */
ADDRESS offset                           /* address offset from base address */
)
{ 
 
  /* Issue unlock sequence command */
  FLASH_WR(base_addr, LLD_UNLOCK_ADDR1, NOR_UNLOCK_DATA1);
  FLASH_WR(base_addr, LLD_UNLOCK_ADDR2, NOR_UNLOCK_DATA2);

  FLASH_WR(base_addr, LLD_UNLOCK_ADDR1, NOR_ERASE_SETUP_CMD);
  
  FLASH_WR(base_addr, LLD_UNLOCK_ADDR1, NOR_UNLOCK_DATA1);
  FLASH_WR(base_addr, LLD_UNLOCK_ADDR2, NOR_UNLOCK_DATA2);

  /* Write Sector Erase Command to Offset */
  FLASH_WR(base_addr, offset, NOR_SECTOR_ERASE_CMD);

  DELAY_US(1);

  while(FlashReadyStatus == 0); //Wait for Ready

}

I measured voltage levels also, during MRAM write/read cycle. Before Word Write,when E W are high, I have on these pins 3.18V - 3.25V. When i want to write my test sequence (1 0 1 0 ...) there is voltage 3.25V, 0V, 3.25V, 0V on data pins... But when i want to read it back i got 0V, 0V, 0V, 0V .... on Data pins. During Word Read i have only one pin high (W 3.25V) others are 0V as written in the datasheet...(I tested this program with good MRAM and when i readed it back i got 3.25V, 0V, 3.25V, 0V so no problem with my program.)

Marek,

Your signal levels look ok.  At this point, I recommend a deeper dive into the MRAM requirements to see if some condition is being violated.

For example, I noticed a power-up sequence in the MRAM datasheet that might need some attention:

Maybe the MRAM is experiencing a dirty reset that would lead to unpredictable behavior.

-Tommy

Tommy, thanks for advices. I soldered pull up resistors for E, W also for CS2, CS3 pins.I coded protection for memories with multiple state flags, so there are no possibility to write at once to flash or mram. Now, im going to burn program to processor and I will see if it helped. I will announce the result to this thread.

Marek,

Good to hear that you have it working now.  Thanks for sharing your solution!

-Tommy