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TMS320F28377D: Custom bootloader for dual-core device.

Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE

Hi all,

My customer is able to design bootloader on F28377S and is wondering how to implement the bootloader on F28377D.

Do we have this kind of document showing the bootloader design procedure for multi-core devices?

Regards,

Luke

  • Luke,

    The information that is published for F28377S boot will have an equivalent in the F28377D documents.

    Is there a specific concern with dual-core boot?

    -Tommy

  • Tommy,

    My customer wants to implement his own bootloader and receive software image via SCI, he is wondering how to program the flash memory of cpu2?

    Do we have document introducing how to implement a flash based bootloader to upgrade both cpu1 and cpu2?

    Luke

  • Luke,

    This might be helpful: ~\C2000Ware_XXXX\device_support\f2837xd\examples\dual\F2837xD_sci_flash_kernels

    -Tommy

  • Tommy,

    Thanks, this example code is helpful.

    Since my customer wants to develop his own bootloader, he should be able to implement his own SCI communication protocol based on this example. And according to this example code, he should develop two bootloaders, one is for CPU1 and the other is for CPU2, is this correct? Do we have flow chart of dual-core firmware upgrade procedure?

    One more question, CPU1 cannot program CPU2's flash memory, is this correct please?

    -Luke

  • Luke Chen said:
    Since my customer wants to develop his own bootloader, he should be able to implement his own SCI communication protocol based on this example. And according to this example code, he should develop two bootloaders, one is for CPU1 and the other is for CPU2, is this correct? Do we have flow chart of dual-core firmware upgrade procedure?

    I am not aware of any diagrams for this, but I did find this appnote that might have some additional information.

    Luke Chen said:
    One more question, CPU1 cannot program CPU2's flash memory, is this correct please?

    Each CPU is only meant to manage its own local bank: