This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28388D: Possibility to implement a multiple phase-leg Interleaved peak-current control by internal resources of the MCU

Part Number: TMS320F28388D

Hi,

analog subsystem of the latest generation of Delfino MCUs (including dual core models F2827xD and F2838xD) features internal ramp generator as well, which in combination with programable comparator (combination of DAC and internal analog comparator) greatly simplifies implementation of PCC (peak-current control) with all its benefits. However, it seems that there is only one ramp generator available (please, correct me if I am mistaken!). Thus, it seems that implementation of a multiple phase-leg Interleaved peak-current control by internal resources of the MCU requires again some additional (external) hardware resources (for generation of compensation slopes, for more independent DAC references etc.). Could you please suggest an effective workaround for this problem (employing minimal amount of external HW resources)?

Best regards

Nenad

  • We have ramp generator for each CMPSS.

    For multiple phase-leg Interleaved peak-current control you still have one voltage loop, right?

    In that case you will have the voltage loop controller output written to multiple DACs. Then you add the slope compensation to each DAC and control the PWM output of each phase.

    Shamim

  • Hi Shamim,

    initially we had single voltage controller loop, and up to four interleaved phase-legs, but over the last two decades we switched to the resonant topologies featuring input stage (grid interface) based on split DC-links, and up to six interleaved phase-legs (up to three input phases) and two optional interleaved channels for battery charger's output stage. 

    In the Technical Reference Manual for latest generation of TI2000 MCUs (e.g. Rev. B for TMS2838xD) there is no explicit indication how many ramp generators and CMPSS subsystems are available, as well as there is no comparison of these peripherals/subsystems among the models within the TMS2837x and TMS2838x series of MCUs.

    There are only three internal DACs available ==> up to three internal programmable comparators can be implemented, assuming that compensation slopes for all required channels are provided externally, isn't it? Thus, there is no elegant possibility (e.g. by SW) to define the compensation slope's specifications (slope's gradient…).

    Additionally, I found within ongoing discussions some reports of unexpected behavior of CMPSS subsystem (when used in combination with cycle-by-cycle trip mode of ePWM units).

    Best regards

    Nenad

      

  • Yes, with three internal DACs you can implement slope compensation for three comparators.

    If you have any issue with CMPSS in CBC mode pls let us know.

    Shamim

  • Dear Shamim,

    the configuration employing three internal DACs enables peak-current control (PCC) with the three comparators (e.g. for three interleaved phases),

    but provides only one slope compensation signal (common to all three channels) because there is only one (internal) ramp generator available, isn't it? Thus, a solution with two independent output stages (two separate DC links, with independently controlled voltages, and PCC controlled currents) is not possible without additional circuitry in the MCUs ecosystem? 

    I have some issues concerning CMPSS in CBC mode: as partially discussed on E2E forum, tackling the fact that CMPSS does not have an option to keep the PWM output in the inactive state (after the CMPSS is triggered within that cycle) till the end of that switching cycle. Correct me if I am mistaken but it seems that only a very short output pulse is generated by CMPSS subsystem instead, indicating that the CMPSS event occurred, but requiring additional intervention to keep the PWM output in the inactive state till the end of that switching cycle.  

    Thus, I would appreciate an example employing CMPSS comparators, ePWM resources (including CBC mode) for implementation of emulated PCC.

    Is there any chance to successfully combine (by CLB subsystem for example), outputs from the analog comparators (CTRIPxH  x=1...8 ; CTRIPxL x=1...8) with some other ePWM outputs, to implement resulting outputs of some specific PWM generator?

    Best regards
    Nenad
  • Dear Shamim,

    is there a possibility to extend the available PCC possibilities, i.e. number of supported phases per DAC (e.g. by comparing its value to the sum of currents as well as comparing the currents each to other, in order to enable CMPSS event only to the PWM channel with highest actual current at the moment)?

    Besides, in Analog Subsystem Block Diagram (e.g. figure 5-26) it is not clear if the ramp generators are independent of each other (i.e. does each CMPSS subsystem features its own ramp generator), as well as DAC12 elements within Comparator (are they independent of DACOUTA, B and C etc.).

    Anyway, what is the maximum capacitive load of ePWM unit outputs (assuming that HRPWM mode is selected), by the R-C reconstruction filter? Assume that an additional DAC outputs (required for PCC applications running at about 40kHz), feature resolution at least as good as that of the internal DACs (12-bit).

    Best regards

    Nenad

  • "In the Technical Reference Manual for latest generation of TI2000 MCUs (e.g. Rev. B for TMS2838xD) there is no explicit indication how many ramp generators and CMPSS subsystems are available, as well as there is no comparison of these peripherals/subsystems among the models within the TMS2837x and TMS2838x series of MCUs."

    While this is not clearly stated the registers for the DACs and Ramps are subjugate to the cmpss registers. Each CMPSS has its own DAC and Ramp register. And if you write something to the CMPSS1 DAC or Rampe register, the CMPSS2 DAC and Ramp are unaffected. So the modules are independent.

  • When trying to find the number of CMPSS modules that are available for a given device family, I recommend using the Device Comparison Table in the datasheet:

    To find out what is available within each CMPSS instance, use the block diagram from the TRM:

    For a comparison of modules across device families, see the C2000 Peripherals Reference Guide:

  • Dear Shamim,

    after another consultation with the manuals (and spotting the corresponding CMPSS block diagram within the TRM , related device comparison...), internal MCU's "resource inventory" dedicated to that subsystem became much more transparent. Now, I just need an appropriate launchpad and/or performance demonstration kit for F28388D model (favorably priced, of course) to verify all my assumptions (ideas on that topic…).

    Best regards

    Nenad

  • Since the "Comparator Subsystem (CMPSS) Module Type Description" table posted by tlee shows that the comparator system is identical to that of the 28004x series you can get a 280049C Launchpad to verify.