Greetings,
In my CLB design, the CLB clock is running at the maximum rate. The design uses two tiles each of which generates a pulse which is one CLB clock wide. These are passed on to a third tile. One of the signals is arriving at the third tile with no issue. The other is not. As far as I can see, they are programmed identically except for the tile which generates them and the AUXSIG each uses. The one which works uses AUXSIG1 and the one which fails uses AUXSIG2. The signal on AUXSIG1 is fed into cell input 0, and the other into cell input 1. They both use the global mux, rising edge detection, and the synchronizer, and the GP register is setup for external input.
The same code runs on our development platform with no issues. But because these are internal signals, I can’t see how the HW could be affecting it.
Debugging it, I can see that the failing signal is being correctly generated at its source. At the destination tile, I have tried to latch the fact that it occurred, and see nothing. If I switch to the other signal, it latches with no issues.
What could I be the difference?
Thank you,
Ed
