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Tool/software: TI C/C++ Compiler
Hello,
I have a question regarding the placement of variables in the RAM. I have defined the following section in my project. The RAMGS0 and RAMGS1 should be used for this.
This section is used by the following variables.
After compilation I get an error from the linker.
The variables need a space of 0x1353 words. The sum of RAMGS0 and RAMGS1 is 0x2000.
Why doesn´t the segment fit into the memory?
Thank you very much
Ralf
Ralf,
It seems like there are other memory sections allocated to RAMGS0 and RAMGS1. If that's the case you will just need to allocated another memory section to this section.
for more information..
Regards,
Ozino
Dear Ozino,
thank you very much for your response.
I have tried to use RAMGS5 and RAMGS6 for the “RMS-Data” section, unfortunately with no success. In my opinion this should be work, because I have used the splitting operator “>>”.
The size of the structures is definitely lower than 0x1000 words.
struct t_data_10ms_ts
{
float sum;
float chk;
unsigned short idx;
float mem[(unsigned short)(10e-3/TS_WR_MAIN + 0.5)]; };
struct t_data_20ms_ts
{
float sum;
float chk;
unsigned short idx;
float mem[(unsigned short)(20e-3/TS_WR_MAIN + 0.5)];
};
TS_WR_MAIN is 62.5µs, so the size of the mem[] fields is 160 and 320 float variables.
Here is the content of my cmd-File:
// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
// RAMM0 : origin = 0x000122, length = 0x0002DE
RAMM0 : origin = 0x000124, length = 0x0002DC // musste geändert werden, Fehler in der C2000 Ware
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
/* RAMLS4 : origin = 0x00A000, length = 0x000800 */
/* RAMLS5 : origin = 0x00A800, length = 0x000800 */
RAMLS4_5 : origin = 0x00A000, length = 0x001000
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
EMIF2_CS0n : origin = 0x90000000, length = 0x10000000
EMIF2_CS2n : origin = 0x00002000, length = 0x00001000
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB | FLASHC PAGE = 0, ALIGN(8), crc_table(_linkerCrcTable, algorithm = CRC32_PRIME)
.text : >> FLASHB | FLASHC PAGE = 0, ALIGN(8), crc_table(_linkerCrcTable, algorithm = CRC32_PRIME)
codestart : > BEGIN PAGE = 0, ALIGN(8), crc_table(_linkerCrcTable, algorithm = CRC32_PRIME)
.stack : > RAMM1 PAGE = 1
.switch : > FLASHB | FLASHC PAGE = 0, ALIGN(8)
.TI.crctab : > FLASHB | FLASHC PAGE = 0
/* Allocate uninitalized data sections: */
#if defined(__TI_EABI__)
.init_array : > FLASHB | FLASHC, PAGE = 0, ALIGN(8)
.bss : > RAMLS2, PAGE = 1
.bss:output : > RAMLS2, PAGE = 1
.data : > RAMLS2, PAGE = 1
.sysmem : > RAMLS2, PAGE = 1
.const : > FLASHB | FLASHC, PAGE = 0, ALIGN(8)
#else
.pinit : > FLASHB | FLASHC, PAGE = 0, ALIGN(8)
.ebss : > RAMLS2, PAGE = 1
.esysmem : > RAMLS2, PAGE = 1
.econst : > FLASHB | FLASHC PAGE = 0, ALIGN(8), crc_table(_linkerCrcTable, algorithm = CRC32_PRIME)
#endif
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
Filter_RegsFile : > RAMGS0, PAGE = 1
.em2_cs0 : > EMIF2_CS0n, PAGE = 1
.em2_cs2 : > EMIF2_CS2n, PAGE = 1
/* CLA specific sections */
#if defined(__TI_EABI__)
Cla1Prog : LOAD = FLASHA,
RUN = RAMLS4_5,
LOAD_START(Cla1funcsLoadStart),
LOAD_END(Cla1funcsLoadEnd),
RUN_START(Cla1funcsRunStart),
LOAD_SIZE(Cla1funcsLoadSize),
PAGE = 0, ALIGN(8)
#else
Cla1Prog : LOAD = FLASHA,
RUN = RAMLS4_5,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0, ALIGN(8), crc_table(_linkerCrcTable, algorithm = CRC32_PRIME)
#endif
CLADataLS0 : > RAMLS0, PAGE=0
CLADataLS1 : > RAMLS1, PAGE=0
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
RMS_Data : >> RAMGS5 | RAMGS6, PAGE = 1
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASHA,
RUN = RAMD0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASHA,
RUN = RAMD0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#else
ramfuncs : LOAD = FLASHA,
RUN = RAMD0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#endif
/* The following section definition are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
/* The following section definition are for IQMATH */
IQmath : > FLASHA, PAGE=0
IQmathTables : > FLASHA, PAGE=0
IQmathTablesRam : > FLASHA, PAGE=0
#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 0
.scratchpad : > RAMLS1, PAGE = 0
.bss_cla : > RAMLS1, PAGE = 0
.const_cla : LOAD = FLASHA,
RUN = RAMLS1,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 0
#endif //CLA_C
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Thank you very much
Ralf
The problem is all the arrays are in the same input section. As described in this part of the larger article Linker Command File Primer, input sections may not be split.
The best solution is to build with the compiler option --gen_data_subsections=on, to put each array in its own subsection. Then splitting would occur. However, there is a compiler bug which prevents this solution from working. I filed the entry EXT_EP-10080 to have this problem investigated. You are welcome to follow it with the link below in my signature.
There is a workaround. Remove the SET_DATA_SECTION pragmas. This causes the compiler to put each array in a subsection of the default section name .ebss. Change the linker command file to have lines similar to these ...
RMS_Data
{
file.obj(.ebss)
} >> RAMGS0 | RAMGS1 PAGE = 1
This creates an output section name RMS_Data. It is made up of one input section named .ebss, from the object file named file.obj. Change file.obj to the name of the object file which defines these arrays. The allocation of RMS_Data is split across the memory ranges RAMGS0 and RAMGS1.
Thanks and regards,
-George