Hello,
I want to create two PWMs on ePWM1 that work in updown mode (I need updown mode because I want to add software deadtime). PWMs are inverted, so when one is high, the other one is low and vice versa. Now, my error is the following: When using updown mode, I can't change duty cycle of one PWM over a certain threshold (around 62%) and I can't lower the other PWM under around 37%. Also, freq of both PWMs is bad, it gets lowered. I can't get the needed duty cycle even if I put duty cycle lower than 62%. So if I want 50% on both PWMs, I will get like 40% on one and like 60% on the other, with freq being 1.7k instead of 2.5k on both. Now, if I use up mode, everything works fine, but I need updown mode. I'm measuring using oscilloscope. Here's my code:
#include "epwm_device.h"
interrupt void isr_epwm2(void)
{
PieCtrlRegs.PIEACK.bit.ACK3 = 1;
EPwm2Regs.ETCLR.bit.INT = 1;
EPwm2Regs.ETCLR.bit.SOCA = 1;
}
void init_epwm()
{
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
//reset PWM1
DevCfgRegs.SOFTPRES2.bit.EPWM1 = 1;
DevCfgRegs.SOFTPRES2.bit.EPWM1 = 0;
//reset PWM2
DevCfgRegs.SOFTPRES2.bit.EPWM2 = 1;
DevCfgRegs.SOFTPRES2.bit.EPWM2 = 0;
EDIS;
//konfiguracija ePWM1
//podesi takt ePWM modula
EPwm1Regs.TBCTL.bit.CLKDIV = 0; //delilac takta 1
//pauziraj PWM tokom pauze u debagovanju
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0;
//pocetni smer brojanja na gore
EPwm1Regs.TBCTL.bit.PHSDIR = START_COUNT_UP;
//omoguci TBPHS registar
EPwm1Regs.TBCTL.bit.PHSEN = 1;
//simetricni PWM (up-down count mode)
EPwm1Regs.TBCTL.bit.CTRMODE = CTR_UPDOWN;
//pocetna faza 0, period 10000 taktova
EPwm1Regs.TBPHS.all = EPWM1_PHASE;
EPwm1Regs.TBPRD = EPWM1_PERIOD;
//podesi compare registre
//registar A mora biti veci za 1000 zbog mrtvog vremena
EPwm1Regs.CMPA.bit.CMPA = EPWM1_CMPA;
EPwm1Regs.CMPB.bit.CMPB = EPWM1_CMPB;
//kanal A - na uzlaznoj ivici HIGH, na silaznoj LOW
//kanal B - suprotno
EPwm1Regs.AQCTLA.bit.CAU = AQ_HIGH;
EPwm1Regs.AQCTLA.bit.CAD = AQ_LOW;
EPwm1Regs.AQCTLB.bit.CBU = AQ_LOW;
EPwm1Regs.AQCTLB.bit.CBD = AQ_HIGH;
// konfiguracija EPWM2
EPwm2Regs.TBCTL.bit.CLKDIV = 0; // delilac takta 1
EPwm2Regs.TBCTL.bit.FREE_SOFT = 0; // blokiraj tokom debug pauze
EPwm2Regs.TBCTL.bit.PHSDIR = START_COUNT_DOWN; // pocetna faza na gore
EPwm2Regs.TBCTL.bit.PHSEN = 1; // omoguci registar faze
EPwm2Regs.TBCTL.bit.CTRMODE = CTR_UP; // up count mod
// pocetna faza 0, period 10000 taktova
EPwm2Regs.TBPHS.all = EPWM2_PHASE;
EPwm2Regs.TBPRD = EPWM2_PERIOD;
// pusti ADC1 SOC na svakom maksimumu brojaca
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // ukljuci SOC A
EPwm2Regs.ETSEL.bit.SOCASEL = 1; // na svaku nulu
EPwm2Regs.ETPS.bit.SOCAPRD = 1;
// prekid da resetuje flagove
EPwm2Regs.ETSEL.bit.INTEN = 1; // ukljuci EPWM2INT
EPwm2Regs.ETSEL.bit.INTSEL = 1; // na svaku nulu
EPwm2Regs.ETPS.bit.INTPRD = 1;
// debug
EPwm2Regs.AQCTLA.bit.ZRO = AQ_TOGGLE; // toggle na nulu
//pustanje kloka na PWMove
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
}
