Dear Champs,
I am asking this for our customer.
1) Is it possible that EPWM event trigger can be overflowed? When overflow, the EPWM SOC will not be triggered for ADC, is that correct?
2) If 1) is yes. Is the user "responsible" to clarify if there is any overflow and to clear the flag or force the event trigger again? Or is there any hardware for that?
3) ETFLG.SOCA/B is cleared "automatically" after the pulse event occurs. Is it right?
4) We are debugging a weird issue, please advise us.
On TI F280025 control card, the SW setting is:
- Use EPWM1 CMPC to generate SOCA to trigger many ADC channels.
- CMPC = CMPA >> 1 (That is, CMPC = 1/2 CMPA, Up-count. Action qualifier: ZRO to clear and CAU to set).
In normal case, it could run well as desired.
When a special event occurred, the user set CMPA to 0 (duty 0), but then all ADC channels failed to sample, which are not desired.
As desired, we thought all ADC should still sample because they were triggered by CMPC=0 during this special event.
When ADC failed to sample, we found it seemed EPWM1 SOCA failed to trigger (that is, it hanged). And the ETFLG.SOCA = 1 remained. We don't know why.
After we forced the SOCA again by ETFRC.SOCA on CCS watch window, then it could work well again. Note that no matter we cleared the SOCA (ETCLR.SOCA) or not before ETFRC.SOCA, it could work well again.
Therefore, we are confused why the EPWM1 SOCA hanged first and then why we could restore it by ETFRC.SOCA.
Do you have any comment?
Wayne Huang
