• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 81 subscribers
  • Views 164 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMDSCNCD28388D: Clock settings

Ravi H
Expert 1475 points
Part Number: TMDSCNCD28388D

Hi,

Im using epwm deadband example. The settings are below:


EPwm1Regs.TBPRD = 5555; // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter

//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//
// Setup compare
//
EPwm1Regs.CMPA.bit.CMPA = 2777;

//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;

EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;

//
// Active Low PWMs - Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED.bit.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED.bit.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;

//
// Interrupt where we will change the Deadband
//
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

From set TBPRD for 200 MHz I should get 18 kHz epwm.

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

PLL settings

// Multipliers and dividers to configure 200MHz SYSPLL output from 25MHz XTAL
//
#define SYS_IMULT IMULT_32
#define SYS_REFDIV REFDIV_2
#define SYS_ODIV ODIV_2
#define SYS_DIV PLLCLK_BY_1

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

But Im getting 9 kHz frequency epwm. So I think PLL output is 100 MHz and not 200 MHz.

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

By changing 

#define SYS_IMULT IMULT_32
#define SYS_REFDIV REFDIV_1
#define SYS_ODIV ODIV_2
#define SYS_DIV PLLCLK_BY_1

or

#define SYS_IMULT IMULT_32
#define SYS_REFDIV REFDIV_2
#define SYS_ODIV ODIV_1
#define SYS_DIV PLLCLK_BY_1

Im getting epwm of 18 kHz, whereby I think PLL clk is at 200 MHz

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

 InitSysPll(XTAL_OSC, SYS_IMULT, SYS_REFDIV, SYS_ODIV, SYS_DIV, SYSCTL_DCC_BASE0);

Second question: what is the use of SYSCTL_DCC_BASE0.

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

Please help me understand this. By set PLL Im not getting required epWM freq.

  • 0
    TI__Guru 51940 points

    You should change the EPWM clock divider to set the divider for the EPWM to 1 isntead of 2. The MCU runs at 200MHz. The EPWM default runs at 100MHz, you have to change the divider to be a 1 instead of a 2.

    The DCC is our clock comparator and is being used to ensure that the clocks are valid and running and not failing. Its a dual clock comparator module checking the status of one clock by comparing it  to another.

  • 0 in reply to Nima Eskandari
    Expert 1475 points

    I had to change,

    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;

    Already the settings were

    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //  TB_DIV1 = 0
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    Please tell me PLLSYSCLK is now set to 200 MHz, can it be increased beyond ? and by how much ?

  • 0 in reply to Ravi H
    TI__Guru 51940 points

    No 200 is max!

    Nima