Hello,
In the datasheet of the F28069 in page 61 the ADC clock max = 80MHz, in page 82 its 40MHz.
In the same datasheet in page 8 its said that the conversion time for each ADC its 325ns, since each conversion takes 13 ADC clock cycles, it gives a frequency of 40MHz.
This means that if we are sampling 5 channels configured with ACQPS=6, which will be 7 ADC clock cycles, this value will be "inside" (page 85 of SPRS698A.pdf) of the previous conversion channel, so we will have a total conversion time in ADC clocks of
7+13*5 = 72 ADC clks
which is 72 * 25n = 1.8ms
Are these calculations correct?
