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TMS320F28379S: retain data during/after watchdog reset?

AnBer
Mastermind 28880 points
Part Number: TMS320F28379S

Team,

Are there some build-in mechanism to retain data during/after WDT reset?
This would be typically used to retrieve the last state (appr. 16 bytes) of a state machine after a WDT reset.
This should work on multiple C2000 (F28379S, F280049, F280025) derivatives.

-I have seen the below post that suggest to use the Flash:
     https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/713476
I looked at the page 258 of the "F2837xD Workshop Workshop Guide and Lab Manual" (located here ).
  - Does it means that 1 full sector need to be kept for such retain mechanism?
  - Is there a risk that the WDT reset will remove power from Flash and damage it?
  - In term of performance (ie speed) I assume the fastest would be to erase 1 block and write a flash area that correspond/is aligned to a complete cache line. Correct?
 -What are the other consideration to take into account?

-Could the CAN RAM be used for this purpose?

-Are there some SW mechanism that upon watch dog reset would for example run an ISR or SWI and wait for completion before applying the XRS signal for reset?

-What would be easiest interface to use if this mechanism is implemented using an external memory or external Flash?

Thanks in advance,
A.

  • 0
    TI__Guru* 93755 points

    Anber,

    Are there some build-in mechanism to retain data during/after WDT reset?

    As Vivek mentions in the other post, RAMs are cleared after a reset. This is also mentioned in

    Table 4-3. Boot ROM Sequence of SPRUHM8I.

      - Does it means that 1 full sector need to be kept for such retain mechanism?

    Correct. The smallest amount of flash that can be erased and re-programmed is a sector.

       - Is there a risk that the WDT reset will remove power from Flash and damage it?
     

    Is the instant when the WD will fire a reset deterministic? Or can it happen randomly?

      -Could the CAN RAM be used for this purpose?

     

    I haven’t tried this myself, but I think it should work.

      -Are there some SW mechanism that upon watch dog reset would for example run an ISR or SWI and wait for completion before applying the XRS signal for reset?
     
    No. For the main WD, it is either reset or interrupt. The NMIWD can be used to reset the device after the delay.

      -What would be easiest interface to use if this mechanism is implemented using an external memory or external Flash?

    [/quote]
     

    SPI flash or EEPROM may be the easiest to interface.

  • 0
    TI__Guru* 84255 points

    Anber,

     Regarding your question "Is there a risk that the WDT reset will remove power from Flash and damage it?"

    If a watchdog reset happens during an active erase operation, the erase operation will fail.  Hence, the erase operation should be repeated to complete the erase successfully.  But, if reset happens during program operation, it can corrupt the flash bit locations that you are trying to program.  Hence, you would need to erase and reprogram.  If the reset happens while programming OTP, note that you will not be able to erase and reprogram it (OTP is not erasable).

    Regarding your question "In term of performance (ie speed) I assume the fastest would be to erase 1 block and write a flash area that correspond/is aligned to a complete cache line. Correct?"

    If you want the data to be present at the same address location all the time, yes, you can do that.  Please note that the max write/erase cycle spec for a sector is 20K (Datasheet has this info).

    Thanks and regards,

    Vamsi