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TMS320F28379S: Setting up the ADC channels in Simulink?

Part Number: TMS320F28379S
Other Parts Discussed in Thread: C2000WARE

Hi,

I'm setting up a model with 24off ADC channels and currently all are permanently set to 0V. If I replace an ADC i/p with a constant, this works fine, so the ADC is not reading correctly.

My device is a TMS320F28379SZWTT and the System Clock is 16MHz and for a 12bit conversion this requires 10.5 ADC clk cycles.

The Simulink ADC Block Parameters options are shown below and I need to know the following:-

SOCx acquisition window => should be a min of 10.5 (so 15 should be ok?)

SOCx trigger Source => should this be set to software?

Any help would be most appreciated..

 

Regards

Ian

  • ian cartwright said:
    System Clock is 16MHz

    This seems like an irregular SYSCLK frequency for a device designed to support 200-MHz SYSCLK.  It is within spec, but quite slow.  Can you confirm this?

    ian cartwright said:
    SOCx acquisition window => should be a min of 10.5 (so 15 should be ok?)

    The acquisition window value only needs to satisfy the >75-ns Sample window duration parameter.

    10.5 ADC clocks refers to the downstream converter state machine that initiates after the ACQPS tSH window shown in the timing diagram.

    ian cartwright said:
    SOCx trigger Source => should this be set to software?

    This depends on your intended scheme.  Software triggering is fine if you only need an instantaneous read point (like temperature sensing) for some background task.  Time-based triggering is more appropriate for control loops or signal processing.

    You can find header-based ADC examples in C2000Ware for reference:  ~\C2000Ware_XXXX\device_support\f2837xs\examples\cpu1

  • Hi, sorry thats not quite correct.

    I'm using external a 16MHz external osc and the spec says 2 to 25MHz.

    I'm assuming this freq is increased to 20MHz via the PLL?

    The SOCx acquisition window is measured in ADC Clk cycles so what should this be set to using an 16Mhz ext / 200MHz PLL?

    Just incl my Simulink H/W clk settings if that helps..

    Many thanks

    Ian

  • ian cartwright said:
    I'm using external a 16MHz external osc and the spec says 2 to 25MHz.

    I'm assuming this freq is increased to 20MHz via the PLL?

    It appears that Simulink is using the PLL to generate 200-MHz SYSCLK, but I could be mistaken.  Simulink is a third party tool so we do not have expertise with it.

    ian cartwright said:
    The SOCx acquisition window is measured in ADC Clk cycles so what should this be set to using an 16Mhz ext / 200MHz PLL?

    The ACQPS window for F2837x is defined using SYSCLK cycles, which appears to be 200-MHz in your scenario.

    The recommended arbitration scheme for resolving information conflicts is Errata >> Datasheet >> TRM >> Other TI Source >> Non-TI Source.

  • Hi,

    I've checked all the documents and its not clear what is the value for ACQPS and ADC clk cycles for the TMS320F28379SZWTT device running with a 200MHz SYSCLK?

    My system clock is 1/200Mhz = 5nS and ACQPS = ? ADCCLK=?

    Many Thanks

    Ian

  • Ian,

    The specific timings are configurable by the developer and should be checked against the datasheet requirements.

    In generalized terms, the SYSCLK frequency matches the CPU frequency and is distributed to the device peripherals like ADC:

    The ADC uses this SYSCLK reference to generate both the ADCCLK:

    and ACQPS-defined acquisition window:

    -Tommy

  • Hi many thanks for the reply, but I'm not sure if I have access to the ADCSOCCTL register and within simulink the options are as below:-

    and the SOCx acquisition window is described as :-

    I've tried setting the SOCx acquisition window to 12/15/64/100 and still get a result of zero.

    Is it possible for you to say what the minimum default SOCx acquisition window would be for my design with a 200Mhz Sysclk?

    Are there any other options I could try and also is there an easy way to try and read the ADC o/p as a scope block is not ideal and I'm currently using a CAN o/p which seems ok. As I said if I replace the ADC with a constant this works fine, so its juts an issue with the ADC block not reading/sampling the voltages correctly.

    Many thanks

    Ian

  • Hi many thanks for the reply, but I'm not sure if I have access to the ADCSOCCTL register and within simulink the options are as below:-

    and the SOCx acquisition window is described as :-

    I've tried setting the SOCx acquisition window to 12/15/64/100 and still get a result of zero.

    Is it possible for you to say what the minimum default SOCx acquisition window would be for my design with a 200Mhz Sysclk?

    Are there any other options I could try and also is there an easy way to try and read the ADC o/p as a scope block is not ideal and I'm currently using a CAN o/p which seems ok. As I said if I replace the ADC with a constant this works fine, so its juts an issue with the ADC block not reading/sampling the voltages correctly.

    Many thanks

    Ian

  • ian cartwright said:
    I'm not sure if I have access to the ADCSOCCTL register and within simulink the options are as below

    My understanding of Simulink is that it will auto-generate the register writes based on your GUI input values.

    ian cartwright said:
    Is it possible for you to say what the minimum default SOCx acquisition window would be for my design with a 200Mhz Sysclk?

    To comply with the DS requirement of >75-ns, ACQPS can be set to (75 / 5) - 1 = 14

    ian cartwright said:
    Are there any other options I could try

    I'd recommend running a known-working example first to find a solid foundation that you can build upon.  A TI EVM running a C2000Ware example is a good starting point.

    If you want to stay in the Simulink environment, I recommend reaching out to Mathworks support.  I assume that they have similar baseline examples that can be run on an EVM.  They would also be in the best position to assist you with any issues that are specific to Simulink.