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TMS320F28035: protection from single event upsets (SEU)

Genius 16285 points
Part Number: TMS320F28035
Other Parts Discussed in Thread: TMS320F28379D, TMS320F280049

Hi all

My customer has below question.

Please review and comment.

Best regards

Ueli

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Does TI have any useful information on protecting processor and peripheral registers from single event upsets (SEU)?

Preferably for the TMS320F28035 but any more general information would also be welcome.

  • Ueli,

    An important point to consider is that most SEU are Soft Errors, that is no permanent change occurs to the device.  So we have to understand the risk of these kind of errors.

    Due to the active state, of the registers(these are not memory, but driven flip/flops are much more immune to soft errors than the RAM on this device.  In the next cycle the error state may be cleared out as the logic is updated.  In either case the best guard from getting too far into an unknown state is using both the internal watchdog as well as making sure the Illegal ISR is defined to catch any non-specified opcodes.

    As I mentioned the RAM, due to its construction, will be most vulnerable to SEUs.  If it is program memory either an incorrect instruction(or illegal) instruction could be fetched.  If data RAM it would be bad data used in the control LAW.

    The flash memory is much more robust (both due to operating at a higher voltage level as well as its method of storage) to SEU, so I would suggest running as much code as possible from that region.

    Some of the newer C2000 devices, like TMS320F28379D, TMS320F280049, have ECC embedded in both the RAM and Flash, to detect or possibly correct the error.  Those device would be more robust than the F28035 in this regard.

    Best,
    Matthew

  • Matthew

    Thank you for the quick reply and for the detailed explanation, this is very helpful.

    Best regards

    Ueli