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LAUNCHXL-F280049C: Reversed PGA's & TDI/TDO remarks

Guru 54027 points
Part Number: LAUNCHXL-F280049C
Other Parts Discussed in Thread: BOOSTXL-DRV8320RS, INA240

Hello all,

Reference:  SPRUIJ3A–November 2018–Revised August 2019

The Boostxl-drv8320 quick start table 3 site 2 functions for PGA2,4,6 inputs are shown reversed order of SOC inputs as remarked in motor SDK 3.1 and older.

Which one is correct the SDK remarks or Table 3? I had been using Table 3 but noted strange issues Lab05 with external current monitors and using the same ADC input order as PGA's were previously assigned. 

Seemingly the order of phase current ADC sampling is an important aspect for space vector commutation to properly function and should be consistently documented as not to confuse the community.

  • Seemingly TDI/TDO should be configured UART0 (SCIA) in the motor SDK drv8320rs currently assigned GPIO pin35/37 hal.c. Yet TDI/TDO do NOT connect to the x49 MCU per the schematic. Oddly XDS110 shows port A being the auxiliary port and did not work as virtual COM3.

    LaunchXL SW4 is then quite alarming for GPIO35/37 in contrast when motor RDK versions has configured JTAG signals TDI/TDO on these same pins. Hence switch 4 notes for ALT GPIO 35/37 make no sense being SW configurations have dominance over hardware designs.

  • According to the schematic TDI/TDO are NOT used or connected on the Target side of x49c MCU So,

        // GPIO35->SCIA-RX->J101 Pin2 XDS110 virtual COM
        // SCIA-RXD (SW4 UART/SW8 XDS)
        GPIO_setMasterCore(35, GPIO_CORE_CPU1);
        GPIO_setPinConfig(GPIO_35_SCIRXDA);
        GPIO_setDirectionMode(35, GPIO_DIR_MODE_IN);
        GPIO_setPadConfig(35, GPIO_PIN_TYPE_STD);
    
        // GPIO37->SCIA-TX->J101 Pin4 XDS110 virtual COM
        // SCIA-TXD (SW4 UART/SW8 XDS)
        GPIO_setMasterCore(37, GPIO_CORE_CPU1);
        GPIO_setPinConfig(GPIO_37_SCITXDA);
        GPIO_setDirectionMode(37, GPIO_DIR_MODE_OUT);
        GPIO_setPadConfig(37, GPIO_PIN_TYPE_STD);

  • The SCI on GOIO35/37 doesn't use in the example project, so we don't configure the GPIO35/37 for SCI and keep these two pins for JTAG as used in other kits. If you want to use site 2 (J5~J8) to connect the boostxl-drv8320 for motor drive and use the virtual COM, you need to configure the S4, S6, and S8 for connecting the GPIO28/29 to BP, and GPIO35/37 to ALT for UART.

    The PGA2/4/6 and CMPSS2/4/6 assignment does not match the order of U/V/W  in the project, the correct order should be as shown below, but it doesn't affect the motor control since the configuration of PGAs and CMPSSs are the same for these three phases. The current sensing for motor drive depends on the connection configuration of ADC pin and PGA that is set correctly and matches the boards.

    // initialize PGA handle
    obj->pgaHandle[0] = PGA2_BASE; //!< the PGA handle
    obj->pgaHandle[1] = PGA6_BASE; //!< the PGA handle
    obj->pgaHandle[2] = PGA4_BASE; //!< the PGA handle

    // initialize CMPSS handle
    obj->cmpssHandle[0] = CMPSS2_BASE; //!< the CMPSS handle
    obj->cmpssHandle[1] = CMPSS6_BASE; //!< the CMPSS handle
    obj->cmpssHandle[2] = CMPSS4_BASE; //!< the CMPSS handle

  • Hello Yanmin

    Why not put a note on SDK GPIO 35/37 to that affect to keep confusion down, it took hours to figure out what nutty thing was done. The project folder hal.c is specific to LaunchXL BoostXL-drv8320Rs so it should not be configured for pins that don't even exist on the PCB. Other wise why have so many folders for specific hardware if hal.c is the same for all hardware. It seems obvious a monitor other than CCS debug can aid in debug make it easy to setup hardware.

    Yanming Luo said:
    The PGA2/4/6 and CMPSS2/4/6 assignment does not match the order of U/V/W  in the project

    That is not what the post states, look at BoostXl-drv8320res Quick Start Guide PDF. GPIO pin assignments site 2 for PGA names in Table 3 are backwards to the SDK software note for each SOC array sample order assignment.

    Which one is correct, table 3 or SDK notes? The current paths for space vector Park/Clarke expect specific order from hardware. Note PGA1 is not in use it is PGA2_IN for the SDK

    Regards

  • The J7 matches BoostXL Table 3 with TRM table 12-1 and PGA1 is obviously a typo in above SDK remarks. Is the below array order correct for SPV Clarke module inputs and Park transforms to sector mapping with BoosXL-drv8320rs?

    Note the INA240 inputs are shown so FE can confirm testing via LaunchXL external ADC input order indeed works with SDK for all customers. Otherwise advise all customer proper WA or not to use external current sensors with magnitude gains >13. Always in the best interest of the community at large.

  • There was more to the post helpful but not exactly the issue.

  • Please refer to the PGA and ADC configuration in the example project that runs the motor well on both sites. We will consider your feedback to fix these problems. Thanks!

  • Good idea since if we reverse them current goes very high. Oddly I could not get GPIO ALT 35/37 via EQUEP directors & switches to RXD/TXD into J101 and User virtual COM. Yet SCIA was previously some how getting COM4 via GPIO 13/40 but not via GPIO 28/29 configured SCIB for TXD/RXD. Seems there could be something odd with schematic noting. Was going by the PCB silk screen for switch settings and schematic review.

  • It's difficult to meet all requirements on the launchpad, we just try our best to consider most of the using cases.  It could be an option as you mentioned above, I will give your feedback to the launchpad designer. Thanks!