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F28335 DMA Pipeline with XINTF

Hiroshi Nomura
Prodigy 150 points
Other Parts Discussed in Thread: TMS320F28335

Hi, Experts,

I'd like to know how the F28335's DMA pipeline (illustrated in Figure 3 on SPRUFB8D) changes when DMA source and/or destination is XINTF.

For instance, with a XINTF zone configured with Lead/Active/Tail timing being 1/3/1 (XTIMCLK=SYSCLK), and use this as DMA source, then "Read SRC data" cycle in the diagram (which takes 2 cycles on the fiture) replaces 5 cycles?   Or it becomes 6 cycles?    How about the case when such XINTF is set to DMA destination? 

 

 

  • 0
    TI__Expert 8500 points

    The DMA baseline is 4 cycles per transfer. Each waitstate on the XINTF (L/A/T) will add a cycle. So, for the 1/3/1 timing above the DMA will take 9 cycles to transfer.

    Regards,
    Dave Foley

     

  • 0 in reply to David Foley
    Prodigy 150 points

    Thank you.  This clarification is highly appreciated. 

  • 0 in reply to Hiroshi Nomura
    Expert 1725 points

    Hi communiTI!

    I would like to use this thread for another question, regarding the TMS320F28335 DMA pipeline specifications.

    There's said that the DMA needs 4 cycles for a single read, than I suppose that the pipeline creates a delay when reading from memory or from an external interface.

    With Pipeline I would think that there's a pipeline delay of 4 cycles and that (burst-) reads need 1 clockcycle, with the result delayed clock 4-cycles. Just like a pipeline-ADC. I would think that when DMA reads 16 words, that this would take 16Read + 4PipelineDelay cycles.

    On a pipeline ADC the sampleresults are delayed by a pipeline because of its architecture, but it's a continuous stream equal to the ADC sys-clock rate.

    Could someone please clear this up?

    Best regards,

    Tjarco Boerkoel

  • 0 in reply to David Foley
    Prodigy 150 points

    Dear Experts,

    I want to clarify something. So even if we use DMA, we still need to assign the minimum required wait cycles for the external interface XINTF, the L/A/T, right? So this makes it longer to read external memory using DMA, right?

    Thanks