EPWM phase lag

Hi,

 I am using TMS320F28335. I want to generate two pair of PWM's.

I configured EPWM1 and EPWM2 in cmplementary mode.

I want to generate a duty cycle in such way that complementary of EPWM1A is EPWM2A.

code is given below

Initialization:

 // Period = 15000 TBCLK counts
 EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;

 // Set Phase register to zero
 EPwm1Regs.TBPHS.half.TBPHS = 0;

 // Clock ratio to SYSCLKOUT
 EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;      
 EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

 // Symmetrical mode
 EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

 // Master module
 EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
 EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

 // Sync down-stream module
 EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
 EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
 EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
 EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
 EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

 // set actions for EPWM1A
 // Set output to high when TBCTR = CMPA while TBCTR incrementing
 EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
 // Set output to high when TBCTR = CMPA while TBCTR incrementing
 EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;

 // enable Dead-band module
 EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

 // Active Hi complementary
 EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;

 // FED = 150 TBCLKs
 EPwm1Regs.DBFED = 300;

 // RED = 150 TBCLKs
 EPwm1Regs.DBRED = 300; 

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
   
 // EPWM Module 2 config

 // Period = 15000 TBCLK counts
 EPwm2Regs.TBPRD = EPWM1_TIMER_TBPRD;

 // Set Phase register to zero
 EPwm2Regs.TBPHS.half.TBPHS = 0;

 // Clock ratio to SYSCLKOUT
 EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;      
 EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

 // Symmetrical mode
 EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

 // Slave module
 EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
 EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

 // sync flow-through
 EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
 EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
 EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
 EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
 EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

 // set actions for EPWM2A

 // Set output to high when TBCTR = CMPA while TBCTR incrementing
 EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; 
 // Set output to Low when TBCTR = CMPA while TBCTR decrementing
 EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;

 // enable Dead-band module 
 EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
 
 // Active Hi complementary
 EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;

 // FED = 150 TBCLKs
 EPwm2Regs.DBFED = 300;
 // RED = 150 TBCLKs
 EPwm2Regs.DBRED = 300; 

 while(1)
   {
  DutyCycle2 = EPWM1_MAX_CMPA - DutyCycle;
  
  EPwm1Regs.CMPA.half.CMPA = DutyCycle;      // Set compare A value
  
  EPwm2Regs.CMPA.half.CMPA = DutyCycle2;  // Set compare A value
 }

Now I am getting some phase lag between EPWM1A and EPWM2B.

Could any one help me in this regard.  

Regards,

Bhanu Prakash Villuri