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concerto c28 boot rom pie reload problem



Dear sir:

we put example code "blinky_c28" to control system ram( using boot rom ipc method). ex.PC --> can bus -> concerto m3 --> ipc -> control system.

Using MASTER_IPC_MTOC_BRANCH_CALL command branch the code.

The led didn't blinky, but when comment the fucntion "InitPieVectTable()",it work correctly.

it seems that the pie vector table can't be reload.

void main(void) {

volatile unsigned long delay;


InitSysCtrl();


InitGpio(); // Skipped for this example
EALLOW;
GpioG1CtrlRegs.GPCDIR.bit.GPIO70 = 1;
EDIS;
GpioG1DataRegs.GPCDAT.bit.GPIO70 = 1;// turn off LED
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;

 InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

InitPieVectTable(); --> comment it will work correctly.


EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;)
{
//
// Turn on LED
//
GpioG1DataRegs.GPCDAT.bit.GPIO70 = 0;
//
// Delay for a bit.
//
for(delay = 0; delay < 2000000; delay++)
{
}

//
// Turn off LED
//
GpioG1DataRegs.GPCDAT.bit.GPIO70 = 1;
//
// Delay for a bit.
//
for(delay = 0; delay < 2000000; delay++)
{
}
}
}

 

  • Hi Mark,

    are you running the device in stand-alone or with JTAG connected is the behavior same in both cases?

    using the MASTER_IPC_MTOC_BRANCH_CALL method can you put a break point at the address where control Subsystem CPU is supposed to start executing the application? When the program control hits the break point - use load symbols to load the blinky_c28 application symbols and go to main() and step through the code through the PIE init and see why it is failing - also can you check what is the BRANCH address you are giving to IPC is it the entry point address or the address of main().

    Also, let us know if you are building and running from RAM or FLASH - I think its RAM, but confirm. Also make sure when running in stand-alone all the C28x RAM(s) are being properly RAM-INIT'd. take a look at "IPCMtoCBootControlSystem" in ipc_util.c - this function takes care of RAM-INIT before sending a boot mode command. You will have to do similar thing before loading any core to C28x RAM(s) from M3 using IPC. If you have CCS connected then this is taken care of by GEL scripts.

    Please let us know if you have any questions.

     

    Best Regards

    santosh

     

  • HI SANTOSH

    Thanks for your replay.

    I'm running the device in stand-alone without JTAG connected.

    How to do debug with on board emulator(xds100) in boot rom ? Could you give me a hint ?

    For my debug experience, I can't debug C_BOOT ROM MTOC IPC Commands, the IPCLiteMtoCDataWrite function return fail.

    But when running the device in stand-alone without jtag connected, it will work.

    Best Regards,

    Mark

  • Hi Mark,

    you wouldn't need to debug bootROM on the device, it is well tested. All you need is put a brek point on the address where your MTOC_IPC_BRANCH command is asking the bootROM to branch to and once it hits the break point, then load your blinkC28x project symbols (Symbols ONLY) and see where it goes.

    We need to findout why the application is not running properly, all bootROM does is, it will branch to the comamnded address properly. If you are not giving the right entry point as branch address then your application will not run properly. Also it is good idea to first make sure the application is running properly by loading it into the C28x RAM using CCS connected to the core first, not sure if you have already checked this.

    Also, can you tell where M3 is loading the C28x application in ? ...in shared RAM or C28x RAM(s)?

    Best Regards

    Santosh

  • Hi Santosh,

    Thanks again for your reply.

    I have already checked,the c28x jump to the entry point that I assign ( 0xB0 ).

    And The M3 is loading the c28x application to c28x RAM,not shared ram.

    When the c28x app run into InitPieVectTable() function, it will back to "idle".

    here is map and cmd file

    ******************************************************************************
                 TMS320C2000 Linker PC v6.1.0                      
    ******************************************************************************
    >> Linked Fri Nov 02 13:29:58 2012
    
    OUTPUT FILE NAME:   <blinky_c28.out>
    ENTRY POINT SYMBOL: "code_start"  address: 00000000
    
    
    MEMORY CONFIGURATION
    
             name            origin    length      used     unused   attr    fill
    ----------------------  --------  ---------  --------  --------  ----  --------
    PAGE 0:
      BEGIN                 00000000   00000040  00000002  0000003e  RWIX
      RAMM0                 000000b0   000003b0  000003a8  00000008  RWIX
      RAML0                 00008000   00001000  000002dc  00000d24  RWIX
      RAML1                 00009000   00001000  00000000  00001000  RWIX
      FPUTABLES             003fd258   000006a0  00000000  000006a0  RWIX
      IQTABLES              003fd8f8   00000b50  00000000  00000b50  RWIX
      IQTABLES2             003fe448   0000008c  00000000  0000008c  RWIX
      IQTABLES3             003fe4d4   000000aa  00000000  000000aa  RWIX
      BOOTROM               003feda8   00001200  00000000  00001200  RWIX
      RESET                 003fffc0   00000002  00000000  00000002  RWIX
    
    PAGE 1:
      BOOT_RSVD             00000002   0000004e  00000000  0000004e  RWIX
      RAMM1                 00000400   00000400  00000200  00000200  RWIX
      DEV_EMU               00000880   00000180  00000048  00000138  RWIX
      CSM                   00000ae0   00000020  00000016  0000000a  RWIX
      ADC1_RESULT           00000b00   00000020  00000010  00000010  RWIX
      ADC2_RESULT           00000b40   00000020  00000010  00000010  RWIX
      CPU_TIMER0            00000c00   00000008  00000008  00000000  RWIX
      CPU_TIMER1            00000c08   00000008  00000008  00000000  RWIX
      CPU_TIMER2            00000c10   00000008  00000008  00000000  RWIX
      PIE_CTRL              00000ce0   00000020  0000001a  00000006  RWIX
      PIE_VECT              00000d00   00000100  00000100  00000000  RWIX
      PIE_VECT_CP           00000e00   00000100  00000100  00000000  RWIX
      DMA                   00001000   00000200  000000e0  00000120  RWIX
      ASYSCTRLCONFIG        00001700   00000080  00000078  00000008  RWIX
      HWBIST                00001780   00000040  00000000  00000040  RWIX
      FLASH_REGS            00004000   00000300  00000182  0000017e  RWIX
      FLASH_ECC             00004300   00000040  00000024  0000001c  RWIX
      M3PLL                 00004400   00000040  00000008  00000038  RWIX
      RAM_REGS              00004900   00000080  0000003e  00000042  RWIX
      RAM_ERR_REGS          00004a00   00000080  0000003e  00000042  RWIX
      CM_MC_IPC             00004e00   00000040  00000040  00000000  RWIX
      MCBSPA                00005000   00000040  00000024  0000001c  RWIX
      EPWM1                 00005100   00000080  00000080  00000000  RWIX
      EPWM2                 00005180   00000080  00000080  00000000  RWIX
      EPWM3                 00005200   00000080  00000080  00000000  RWIX
      EPWM4                 00005280   00000080  00000080  00000000  RWIX
      EPWM5                 00005300   00000080  00000080  00000000  RWIX
      EPWM6                 00005380   00000080  00000080  00000000  RWIX
      EPWM7                 00005400   00000080  00000080  00000000  RWIX
      EPWM8                 00005480   00000080  00000080  00000000  RWIX
      EPWM9                 00005500   00000080  00000080  00000000  RWIX
      ECAP1                 00005a00   00000020  00000020  00000000  RWIX
      ECAP2                 00005a20   00000020  00000020  00000000  RWIX
      ECAP3                 00005a40   00000020  00000020  00000000  RWIX
      ECAP4                 00005a60   00000020  00000020  00000000  RWIX
      ECAP5                 00005a80   00000020  00000020  00000000  RWIX
      ECAP6                 00005aa0   00000020  00000020  00000000  RWIX
      EQEP1                 00005b00   00000040  00000022  0000001e  RWIX
      EQEP2                 00005b40   00000040  00000022  0000001e  RWIX
      EQEP3                 00005b80   00000040  00000022  0000001e  RWIX
      GPIOG1CTRL            00005f80   00000040  00000040  00000000  RWIX
      GPIOG1DAT             00005fc0   00000020  00000020  00000000  RWIX
      GPIOG1TRIP            00005fe0   00000020  00000020  00000000  RWIX
      COMP1                 00006400   00000020  00000007  00000019  RWIX
      COMP2                 00006420   00000020  00000007  00000019  RWIX
      COMP3                 00006440   00000020  00000007  00000019  RWIX
      COMP4                 00006460   00000020  00000007  00000019  RWIX
      COMP5                 00006480   00000020  00000007  00000019  RWIX
      COMP6                 000064a0   00000020  00000007  00000019  RWIX
      GPIOG2CTRL            00006f80   00000040  0000003c  00000004  RWIX
      GPIOG2DAT             00006fc0   00000020  00000020  00000000  RWIX
      SYSTEM                00007010   00000020  0000001d  00000003  RWIX
      SPIA                  00007040   00000010  00000010  00000000  RWIX
      SCIA                  00007050   00000010  00000010  00000000  RWIX
      NMIINTRUPT            00007060   00000010  00000006  0000000a  RWIX
      XINTRUPT              00007070   00000010  00000010  00000000  RWIX
      ADC1                  00007100   00000080  00000050  00000030  RWIX
      ADC2                  00007180   00000080  00000050  00000030  RWIX
      I2CA                  00007900   00000040  00000022  0000001e  RWIX
      RAML2                 0000a000   00001000  00000020  00000fe0  RWIX
      RAML3                 0000b000   00001000  00000000  00001000  RWIX
      CTOMRAM               0003f800   00000380  00000000  00000380  RWIX
      MTOCRAM               0003fc00   00000380  00000000  00000380  RWIX
      FLASH_EXE_ONLY        0013fff2   00000002  00000002  00000000  RWIX
      ECSL_PWL              0013fff4   00000004  00000004  00000000  RWIX
      CSM_PWL               0013fff8   00000008  00000008  00000000  RWIX
    
    
    SECTION ALLOCATION MAP
    
     output                                  attributes/
    section   page    origin      length       input sections
    --------  ----  ----------  ----------   ----------------
    .pinit     0    000000b0    00000000     UNINITIALIZED
    
    codestart 
    *          0    00000000    00000002     
                      00000000    00000002     F28M35x_CodeStartBranch.obj (codestart)
    
    .initMain 
    *          0    000000b0    0000003c     
                      000000b0    0000003c     blinky_c28.obj (.initMain)
    
    .text.1    0    000000ec    0000036c     
                      000000ec    00000363     F28M35x_DefaultIsr.obj (.text:retain)
                      0000044f    00000009     rts2800_fpu32.lib : _lock.obj (.text)
    
    .text.2    0    00008000    00000260     
                      00008000    000000f9     F28M35x_SysCtrl.obj (.text)
                      000080f9    0000007c     F28M35x_CpuTimers.obj (.text)
                      00008175    00000046     rts2800_fpu32.lib : boot.obj (.text)
                      000081bb    0000002d     F28M35x_PieCtrl.obj (.text)
                      000081e8    00000026     F28M35x_Gpio.obj (.text)
                      0000820e    00000020     F28M35x_PieVect.obj (.text)
                      0000822e    00000019     rts2800_fpu32.lib : args_main.obj (.text)
                      00008247    00000019                       : exit.obj (.text)
    
    ramfuncs   0    00008260    00000066     
                      00008260    00000066     F28M35x_SysCtrl.obj (ramfuncs)
    
    .cinit     0    000082c6    00000016     
                      000082c6    0000000a     rts2800_fpu32.lib : _lock.obj (.cinit)
                      000082d0    0000000a                       : exit.obj (.cinit)
                      000082da    00000002     --HOLE-- [fill = 0]
    
    GETBUFFER 
    *          0    0003fc00    00000000     DSECT
    
    GETWRITEIDX 
    *          0    0003fc00    00000000     DSECT
    
    PUTREADIDX 
    *          0    0003fc00    00000000     DSECT
    
    .reset     0    003fffc0    00000002     DSECT
                      003fffc0    00000002     rts2800_fpu32.lib : boot.obj (.reset)
    
    .econst    1    00000400    00000100     
                      00000400    00000100     F28M35x_PieVect.obj (.econst)
    
    .stack     1    00000500    00000100     UNINITIALIZED
                      00000500    00000100     --HOLE--
    
    DevEmuRegsFile 
    *          1    00000880    00000048     UNINITIALIZED
                      00000880    00000048     F28M35x_GlobalVariableDefs.obj (DevEmuRegsFile)
    
    CsmRegsFile 
    *          1    00000ae0    00000016     UNINITIALIZED
                      00000ae0    00000016     F28M35x_GlobalVariableDefs.obj (CsmRegsFile)
    
    AdcResultFile 
    *          1    00000b00    00000010     UNINITIALIZED
                      00000b00    00000010     F28M35x_GlobalVariableDefs.obj (AdcResultFile)
    
    Adc1ResultFile 
    *          1    00000b00    00000010     UNINITIALIZED
                      00000b00    00000010     F28M35x_GlobalVariableDefs.obj (Adc1ResultFile)
    
    Adc2ResultFile 
    *          1    00000b40    00000010     UNINITIALIZED
                      00000b40    00000010     F28M35x_GlobalVariableDefs.obj (Adc2ResultFile)
    
    CpuTimer0RegsFile 
    *          1    00000c00    00000008     UNINITIALIZED
                      00000c00    00000008     F28M35x_GlobalVariableDefs.obj (CpuTimer0RegsFile)
    
    CpuTimer1RegsFile 
    *          1    00000c08    00000008     UNINITIALIZED
                      00000c08    00000008     F28M35x_GlobalVariableDefs.obj (CpuTimer1RegsFile)
    
    CpuTimer2RegsFile 
    *          1    00000c10    00000008     UNINITIALIZED
                      00000c10    00000008     F28M35x_GlobalVariableDefs.obj (CpuTimer2RegsFile)
    
    PieCtrlRegsFile 
    *          1    00000ce0    0000001a     UNINITIALIZED
                      00000ce0    0000001a     F28M35x_GlobalVariableDefs.obj (PieCtrlRegsFile)
    
    PieVectTableFile 
    *          1    00000d00    00000100     UNINITIALIZED
                      00000d00    00000100     F28M35x_GlobalVariableDefs.obj (PieVectTableFile)
    
    EmuKeyVar 
    *          1    00000d00    00000000     UNINITIALIZED
    
    EmuBModeVar 
    *          1    00000d00    00000000     UNINITIALIZED
    
    FlashCallbackVar 
    *          1    00000d00    00000000     UNINITIALIZED
    
    FlashScalingVar 
    *          1    00000d00    00000000     UNINITIALIZED
    
    PieVectTableCopyFile 
    *          1    00000e00    00000100     UNINITIALIZED
                      00000e00    00000100     F28M35x_GlobalVariableDefs.obj (PieVectTableCopyFile)
    
    DmaRegsFile 
    *          1    00001000    000000e0     UNINITIALIZED
                      00001000    000000e0     F28M35x_GlobalVariableDefs.obj (DmaRegsFile)
    
    AnalogSysctrlRegsFile 
    *          1    00001700    00000078     UNINITIALIZED
                      00001700    00000078     F28M35x_GlobalVariableDefs.obj (AnalogSysctrlRegsFile)
    
    FlashCtrlRegsFile 
    *          1    00004000    00000182     UNINITIALIZED
                      00004000    00000182     F28M35x_GlobalVariableDefs.obj (FlashCtrlRegsFile)
    
    FlashEccRegsFile 
    *          1    00004300    00000024     UNINITIALIZED
                      00004300    00000024     F28M35x_GlobalVariableDefs.obj (FlashEccRegsFile)
    
    M3PllRegsFile 
    *          1    00004400    00000008     UNINITIALIZED
                      00004400    00000008     F28M35x_GlobalVariableDefs.obj (M3PllRegsFile)
    
    RAMRegsFile 
    *          1    00004900    0000003e     UNINITIALIZED
                      00004900    0000003e     F28M35x_GlobalVariableDefs.obj (RAMRegsFile)
    
    RAMErrRegsFile 
    *          1    00004a00    0000003e     UNINITIALIZED
                      00004a00    0000003e     F28M35x_GlobalVariableDefs.obj (RAMErrRegsFile)
    
    CtoMIpcRegsFile 
    *          1    00004e00    00000040     UNINITIALIZED
                      00004e00    00000040     F28M35x_GlobalVariableDefs.obj (CtoMIpcRegsFile)
    
    McbspaRegsFile 
    *          1    00005000    00000024     UNINITIALIZED
                      00005000    00000024     F28M35x_GlobalVariableDefs.obj (McbspaRegsFile)
    
    EPwm1RegsFile 
    *          1    00005100    00000080     UNINITIALIZED
                      00005100    00000080     F28M35x_GlobalVariableDefs.obj (EPwm1RegsFile)
    
    EPwm2RegsFile 
    *          1    00005180    00000080     UNINITIALIZED
                      00005180    00000080     F28M35x_GlobalVariableDefs.obj (EPwm2RegsFile)
    
    EPwm3RegsFile 
    *          1    00005200    00000080     UNINITIALIZED
                      00005200    00000080     F28M35x_GlobalVariableDefs.obj (EPwm3RegsFile)
    
    EPwm4RegsFile 
    *          1    00005280    00000080     UNINITIALIZED
                      00005280    00000080     F28M35x_GlobalVariableDefs.obj (EPwm4RegsFile)
    
    EPwm5RegsFile 
    *          1    00005300    00000080     UNINITIALIZED
                      00005300    00000080     F28M35x_GlobalVariableDefs.obj (EPwm5RegsFile)
    
    EPwm6RegsFile 
    *          1    00005380    00000080     UNINITIALIZED
                      00005380    00000080     F28M35x_GlobalVariableDefs.obj (EPwm6RegsFile)
    
    EPwm7RegsFile 
    *          1    00005400    00000080     UNINITIALIZED
                      00005400    00000080     F28M35x_GlobalVariableDefs.obj (EPwm7RegsFile)
    
    EPwm8RegsFile 
    *          1    00005480    00000080     UNINITIALIZED
                      00005480    00000080     F28M35x_GlobalVariableDefs.obj (EPwm8RegsFile)
    
    EPwm9RegsFile 
    *          1    00005500    00000080     UNINITIALIZED
                      00005500    00000080     F28M35x_GlobalVariableDefs.obj (EPwm9RegsFile)
    
    ECap1RegsFile 
    *          1    00005a00    00000020     UNINITIALIZED
                      00005a00    00000020     F28M35x_GlobalVariableDefs.obj (ECap1RegsFile)
    
    ECap2RegsFile 
    *          1    00005a20    00000020     UNINITIALIZED
                      00005a20    00000020     F28M35x_GlobalVariableDefs.obj (ECap2RegsFile)
    
    ECap3RegsFile 
    *          1    00005a40    00000020     UNINITIALIZED
                      00005a40    00000020     F28M35x_GlobalVariableDefs.obj (ECap3RegsFile)
    
    ECap4RegsFile 
    *          1    00005a60    00000020     UNINITIALIZED
                      00005a60    00000020     F28M35x_GlobalVariableDefs.obj (ECap4RegsFile)
    
    ECap5RegsFile 
    *          1    00005a80    00000020     UNINITIALIZED
                      00005a80    00000020     F28M35x_GlobalVariableDefs.obj (ECap5RegsFile)
    
    ECap6RegsFile 
    *          1    00005aa0    00000020     UNINITIALIZED
                      00005aa0    00000020     F28M35x_GlobalVariableDefs.obj (ECap6RegsFile)
    
    EQep1RegsFile 
    *          1    00005b00    00000022     UNINITIALIZED
                      00005b00    00000022     F28M35x_GlobalVariableDefs.obj (EQep1RegsFile)
    
    EQep2RegsFile 
    *          1    00005b40    00000022     UNINITIALIZED
                      00005b40    00000022     F28M35x_GlobalVariableDefs.obj (EQep2RegsFile)
    
    EQep3RegsFile 
    *          1    00005b80    00000022     UNINITIALIZED
                      00005b80    00000022     F28M35x_GlobalVariableDefs.obj (EQep3RegsFile)
    
    GpioCtrlRegsFile 
    *          1    00005f80    00000040     UNINITIALIZED
                      00005f80    00000040     F28M35x_GlobalVariableDefs.obj (GpioCtrlRegsFile)
    
    GpioG1CtrlRegsFile 
    *          1    00005f80    00000040     UNINITIALIZED
                      00005f80    00000040     F28M35x_GlobalVariableDefs.obj (GpioG1CtrlRegsFile)
    
    GpioDataRegsFile 
    *          1    00005fc0    00000020     UNINITIALIZED
                      00005fc0    00000020     F28M35x_GlobalVariableDefs.obj (GpioDataRegsFile)
    
    GpioG1DataRegsFile 
    *          1    00005fc0    00000020     UNINITIALIZED
                      00005fc0    00000020     F28M35x_GlobalVariableDefs.obj (GpioG1DataRegsFile)
    
    GpioTripRegsFile 
    *          1    00005fe0    00000020     UNINITIALIZED
                      00005fe0    00000020     F28M35x_GlobalVariableDefs.obj (GpioTripRegsFile)
    
    GpioG1TripRegsFile 
    *          1    00005fe0    00000020     UNINITIALIZED
                      00005fe0    00000020     F28M35x_GlobalVariableDefs.obj (GpioG1TripRegsFile)
    
    Comp1RegsFile 
    *          1    00006400    00000007     UNINITIALIZED
                      00006400    00000007     F28M35x_GlobalVariableDefs.obj (Comp1RegsFile)
    
    Comp2RegsFile 
    *          1    00006420    00000007     UNINITIALIZED
                      00006420    00000007     F28M35x_GlobalVariableDefs.obj (Comp2RegsFile)
    
    Comp3RegsFile 
    *          1    00006440    00000007     UNINITIALIZED
                      00006440    00000007     F28M35x_GlobalVariableDefs.obj (Comp3RegsFile)
    
    Comp4RegsFile 
    *          1    00006460    00000007     UNINITIALIZED
                      00006460    00000007     F28M35x_GlobalVariableDefs.obj (Comp4RegsFile)
    
    Comp5RegsFile 
    *          1    00006480    00000007     UNINITIALIZED
                      00006480    00000007     F28M35x_GlobalVariableDefs.obj (Comp5RegsFile)
    
    Comp6RegsFile 
    *          1    000064a0    00000007     UNINITIALIZED
                      000064a0    00000007     F28M35x_GlobalVariableDefs.obj (Comp6RegsFile)
    
    GpioG2CtrlRegsFile 
    *          1    00006f80    0000003c     UNINITIALIZED
                      00006f80    0000003c     F28M35x_GlobalVariableDefs.obj (GpioG2CtrlRegsFile)
    
    GpioG2DataRegsFile 
    *          1    00006fc0    00000020     UNINITIALIZED
                      00006fc0    00000020     F28M35x_GlobalVariableDefs.obj (GpioG2DataRegsFile)
    
    SysCtrlRegsFile 
    *          1    00007010    0000001d     UNINITIALIZED
                      00007010    0000001d     F28M35x_GlobalVariableDefs.obj (SysCtrlRegsFile)
    
    SpiaRegsFile 
    *          1    00007040    00000010     UNINITIALIZED
                      00007040    00000010     F28M35x_GlobalVariableDefs.obj (SpiaRegsFile)
    
    SciaRegsFile 
    *          1    00007050    00000010     UNINITIALIZED
                      00007050    00000010     F28M35x_GlobalVariableDefs.obj (SciaRegsFile)
    
    NmiIntruptRegsFile 
    *          1    00007060    00000006     UNINITIALIZED
                      00007060    00000006     F28M35x_GlobalVariableDefs.obj (NmiIntruptRegsFile)
    
    XIntruptRegsFile 
    *          1    00007070    00000010     UNINITIALIZED
                      00007070    00000010     F28M35x_GlobalVariableDefs.obj (XIntruptRegsFile)
    
    AdcRegsFile 
    *          1    00007100    00000050     UNINITIALIZED
                      00007100    00000050     F28M35x_GlobalVariableDefs.obj (AdcRegsFile)
    
    Adc1RegsFile 
    *          1    00007100    00000050     UNINITIALIZED
                      00007100    00000050     F28M35x_GlobalVariableDefs.obj (Adc1RegsFile)
    
    Adc2RegsFile 
    *          1    00007180    00000050     UNINITIALIZED
                      00007180    00000050     F28M35x_GlobalVariableDefs.obj (Adc2RegsFile)
    
    I2caRegsFile 
    *          1    00007900    00000022     UNINITIALIZED
                      00007900    00000022     F28M35x_GlobalVariableDefs.obj (I2caRegsFile)
    
    .ebss      1    0000a000    00000020     UNINITIALIZED
                      0000a000    00000018     F28M35x_CpuTimers.obj (.ebss)
                      0000a018    00000004     rts2800_fpu32.lib : _lock.obj (.ebss)
                      0000a01c    00000004                       : exit.obj (.ebss)
    
    FlashExeOnlyFile 
    *          1    0013fff2    00000002     UNINITIALIZED
                      0013fff2    00000002     F28M35x_GlobalVariableDefs.obj (FlashExeOnlyFile)
    
    EcslPwlFile 
    *          1    0013fff4    00000004     UNINITIALIZED
                      0013fff4    00000004     F28M35x_GlobalVariableDefs.obj (EcslPwlFile)
    
    CsmPwlFile 
    *          1    0013fff8    00000008     UNINITIALIZED
                      0013fff8    00000008     F28M35x_GlobalVariableDefs.obj (CsmPwlFile)
    
    
    GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name 
    
    address    name
    --------   ----
    ffffffff   .text
    00008247   C$$EXIT
    000001aa   _ADCINT1_ISR
    000001b4   _ADCINT2_ISR
    00000380   _ADCINT3_ISR
    0000038a   _ADCINT4_ISR
    00000394   _ADCINT5_ISR
    0000039e   _ADCINT6_ISR
    000003a8   _ADCINT7_ISR
    000003b2   _ADCINT8_ISR
    00007100   _Adc1Regs
    00000b00   _Adc1Result
    00007180   _Adc2Regs
    00000b40   _Adc2Result
    00007100   _AdcRegs
    00000b00   _AdcResult
    00001700   _AnalogSysctrlRegs
    000003f8   _CFLFSM_ISR
    000003ee   _CFLSINGERR_ISR
    0000040c   _CRAMACCVIOL_ISR
    00000402   _CRAMSINGERR_ISR
    000080e1   _CSMSecurityStatus
    00006400   _Comp1Regs
    00006420   _Comp2Regs
    00006440   _Comp3Regs
    00006460   _Comp4Regs
    00006480   _Comp5Regs
    000064a0   _Comp6Regs
    0000813a   _ConfigCpuTimer
    0000a010   _CpuTimer0
    00000c00   _CpuTimer0Regs
    0000a000   _CpuTimer1
    00000c08   _CpuTimer1Regs
    0000a008   _CpuTimer2
    00000c10   _CpuTimer2Regs
    0013fff8   _CsmPwl
    00000ae0   _CsmRegs
    0000808e   _CsmUnlock
    00004e00   _CtoMIpcRegs
    00000100   _DATALOG_ISR
    0000031c   _DINTCH1_ISR
    00000326   _DINTCH2_ISR
    00000330   _DINTCH3_ISR
    0000033a   _DINTCH4_ISR
    00000344   _DINTCH5_ISR
    0000034e   _DINTCH6_ISR
    00000880   _DevEmuRegs
    00001000   _DmaRegs
    00000286   _ECAP1_INT_ISR
    00000290   _ECAP2_INT_ISR
    0000029a   _ECAP3_INT_ISR
    000002a4   _ECAP4_INT_ISR
    000002ae   _ECAP5_INT_ISR
    000002b8   _ECAP6_INT_ISR
    000080ed   _ECSLSecurityStatus
    00005a00   _ECap1Regs
    00005a20   _ECap2Regs
    00005a40   _ECap3Regs
    00005a60   _ECap4Regs
    00005a80   _ECap5Regs
    00005aa0   _ECap6Regs
    0000042a   _EMPTY_ISR
    00000114   _EMUINT_ISR
    00000236   _EPWM1_INT_ISR
    000001e6   _EPWM1_TZINT_ISR
    00000240   _EPWM2_INT_ISR
    000001f0   _EPWM2_TZINT_ISR
    0000024a   _EPWM3_INT_ISR
    000001fa   _EPWM3_TZINT_ISR
    00000254   _EPWM4_INT_ISR
    00000204   _EPWM4_TZINT_ISR
    0000025e   _EPWM5_INT_ISR
    0000020e   _EPWM5_TZINT_ISR
    00000268   _EPWM6_INT_ISR
    00000218   _EPWM6_TZINT_ISR
    00000272   _EPWM7_INT_ISR
    00000222   _EPWM7_TZINT_ISR
    0000027c   _EPWM8_INT_ISR
    0000022c   _EPWM8_TZINT_ISR
    000002ea   _EPWM9_INT_ISR
    000002c2   _EPWM9_TZINT_ISR
    00005100   _EPwm1Regs
    00005180   _EPwm2Regs
    00005200   _EPwm3Regs
    00005280   _EPwm4Regs
    00005300   _EPwm5Regs
    00005380   _EPwm6Regs
    00005400   _EPwm7Regs
    00005480   _EPwm8Regs
    00005500   _EPwm9Regs
    000002cc   _EQEP1_INT_ISR
    000002d6   _EQEP2_INT_ISR
    000002e0   _EQEP3_INT_ISR
    00005b00   _EQep1Regs
    00005b40   _EQep2Regs
    00005b80   _EQep3Regs
    0013fff4   _EcslPwl
    000080af   _EcslUnlock
    000081df   _EnableInterrupts
    00004000   _FlashCtrlRegs
    00004300   _FlashEccRegs
    0013fff2   _FlashExeOnly
    000082ae   _FlashGainPump
    000082bb   _FlashLeavePump
    000080ce   _GetEXEstatus
    00005f80   _GpioCtrlRegs
    00005fc0   _GpioDataRegs
    00005f80   _GpioG1CtrlRegs
    00005fc0   _GpioG1DataRegs
    00005fe0   _GpioG1TripRegs
    00006f80   _GpioG2CtrlRegs
    00006fc0   _GpioG2DataRegs
    00005fe0   _GpioTripRegs
    00000358   _I2CINT1A_ISR
    00000362   _I2CINT2A_ISR
    00007900   _I2caRegs
    00000128   _ILLEGAL_ISR
    000000ec   _INT13_ISR
    000000f6   _INT14_ISR
    000080f9   _InitCpuTimers
    00008260   _InitFlash
    000081e8   _InitGpio
    00008032   _InitPeripheralClocks
    000081bb   _InitPieCtrl
    0000820e   _InitPieVectTable
    00008000   _InitSysCtrl
    00000420   _LUF_ISR
    00000416   _LVF_ISR
    000080c6   _LockDevice
    00004400   _M3PllRegs
    00000308   _MRINTA_ISR
    000003bc   _MTOCIPC_INT1_ISR
    000003c6   _MTOCIPC_INT2_ISR
    000003d0   _MTOCIPC_INT3_ISR
    000003da   _MTOCIPC_INT4_ISR
    00000312   _MXINTA_ISR
    00005000   _McbspaRegs
    0000011e   _NMI_ISR
    00007060   _NmiIntruptRegs
    00000437   _PIE_RESERVED
    00000ce0   _PieCtrlRegs
    00000d00   _PieVectTable
    00000e00   _PieVectTableCopy
    00000400   _PieVectTableInit
    00004a00   _RAMErrRegs
    00004900   _RAMRegs
    0000010a   _RTOSINT_ISR
    0000036c   _SCIRXINTA_ISR
    00000376   _SCITXINTA_ISR
    000002f4   _SPIRXINTA_ISR
    000002fe   _SPITXINTA_ISR
    00007050   _SciaRegs
    00008285   _SetupFlash
    00007040   _SpiaRegs
    00007010   _SysCtrlRegs
    000001d2   _TINT0_ISR
    0000018c   _USER10_ISR
    00000196   _USER11_ISR
    000001a0   _USER12_ISR
    00000132   _USER1_ISR
    0000013c   _USER2_ISR
    00000146   _USER3_ISR
    00000150   _USER4_ISR
    0000015a   _USER5_ISR
    00000164   _USER6_ISR
    0000016e   _USER7_ISR
    00000178   _USER8_ISR
    00000182   _USER9_ISR
    000001dc   _WAKEINT_ISR
    000001be   _XINT1_ISR
    000001c8   _XINT2_ISR
    000003e4   _XINT3_ISR
    00007070   _XIntruptRegs
    00000600   __STACK_END
    00000100   __STACK_SIZE
    00000001   __TI_args_main
    ffffffff   ___binit__
    ffffffff   ___c_args__
    000082c6   ___cinit__
    ffffffff   ___etext__
    ffffffff   ___pinit__
    ffffffff   ___text__
    0000822e   __args_main
    0000a01c   __cleanup_ptr
    0000a01e   __dtors_ptr
    0000a01a   __lock
    00000457   __nop
    00000453   __register_lock
    0000044f   __register_unlock
    00000500   __stack
    0000a018   __unlock
    00008247   _abort
    00008175   _c_int00
    00008249   _exit
    000000b0   _main
    00000445   _rsvd_ISR
    ffffffff   binit
    000082c6   cinit
    00000000   code_start
    ffffffff   etext
    ffffffff   pinit
    
    
    GLOBAL SYMBOLS: SORTED BY Symbol Address 
    
    address    name
    --------   ----
    00000000   code_start
    00000001   __TI_args_main
    000000b0   _main
    000000ec   _INT13_ISR
    000000f6   _INT14_ISR
    00000100   _DATALOG_ISR
    00000100   __STACK_SIZE
    0000010a   _RTOSINT_ISR
    00000114   _EMUINT_ISR
    0000011e   _NMI_ISR
    00000128   _ILLEGAL_ISR
    00000132   _USER1_ISR
    0000013c   _USER2_ISR
    00000146   _USER3_ISR
    00000150   _USER4_ISR
    0000015a   _USER5_ISR
    00000164   _USER6_ISR
    0000016e   _USER7_ISR
    00000178   _USER8_ISR
    00000182   _USER9_ISR
    0000018c   _USER10_ISR
    00000196   _USER11_ISR
    000001a0   _USER12_ISR
    000001aa   _ADCINT1_ISR
    000001b4   _ADCINT2_ISR
    000001be   _XINT1_ISR
    000001c8   _XINT2_ISR
    000001d2   _TINT0_ISR
    000001dc   _WAKEINT_ISR
    000001e6   _EPWM1_TZINT_ISR
    000001f0   _EPWM2_TZINT_ISR
    000001fa   _EPWM3_TZINT_ISR
    00000204   _EPWM4_TZINT_ISR
    0000020e   _EPWM5_TZINT_ISR
    00000218   _EPWM6_TZINT_ISR
    00000222   _EPWM7_TZINT_ISR
    0000022c   _EPWM8_TZINT_ISR
    00000236   _EPWM1_INT_ISR
    00000240   _EPWM2_INT_ISR
    0000024a   _EPWM3_INT_ISR
    00000254   _EPWM4_INT_ISR
    0000025e   _EPWM5_INT_ISR
    00000268   _EPWM6_INT_ISR
    00000272   _EPWM7_INT_ISR
    0000027c   _EPWM8_INT_ISR
    00000286   _ECAP1_INT_ISR
    00000290   _ECAP2_INT_ISR
    0000029a   _ECAP3_INT_ISR
    000002a4   _ECAP4_INT_ISR
    000002ae   _ECAP5_INT_ISR
    000002b8   _ECAP6_INT_ISR
    000002c2   _EPWM9_TZINT_ISR
    000002cc   _EQEP1_INT_ISR
    000002d6   _EQEP2_INT_ISR
    000002e0   _EQEP3_INT_ISR
    000002ea   _EPWM9_INT_ISR
    000002f4   _SPIRXINTA_ISR
    000002fe   _SPITXINTA_ISR
    00000308   _MRINTA_ISR
    00000312   _MXINTA_ISR
    0000031c   _DINTCH1_ISR
    00000326   _DINTCH2_ISR
    00000330   _DINTCH3_ISR
    0000033a   _DINTCH4_ISR
    00000344   _DINTCH5_ISR
    0000034e   _DINTCH6_ISR
    00000358   _I2CINT1A_ISR
    00000362   _I2CINT2A_ISR
    0000036c   _SCIRXINTA_ISR
    00000376   _SCITXINTA_ISR
    00000380   _ADCINT3_ISR
    0000038a   _ADCINT4_ISR
    00000394   _ADCINT5_ISR
    0000039e   _ADCINT6_ISR
    000003a8   _ADCINT7_ISR
    000003b2   _ADCINT8_ISR
    000003bc   _MTOCIPC_INT1_ISR
    000003c6   _MTOCIPC_INT2_ISR
    000003d0   _MTOCIPC_INT3_ISR
    000003da   _MTOCIPC_INT4_ISR
    000003e4   _XINT3_ISR
    000003ee   _CFLSINGERR_ISR
    000003f8   _CFLFSM_ISR
    00000400   _PieVectTableInit
    00000402   _CRAMSINGERR_ISR
    0000040c   _CRAMACCVIOL_ISR
    00000416   _LVF_ISR
    00000420   _LUF_ISR
    0000042a   _EMPTY_ISR
    00000437   _PIE_RESERVED
    00000445   _rsvd_ISR
    0000044f   __register_unlock
    00000453   __register_lock
    00000457   __nop
    00000500   __stack
    00000600   __STACK_END
    00000880   _DevEmuRegs
    00000ae0   _CsmRegs
    00000b00   _Adc1Result
    00000b00   _AdcResult
    00000b40   _Adc2Result
    00000c00   _CpuTimer0Regs
    00000c08   _CpuTimer1Regs
    00000c10   _CpuTimer2Regs
    00000ce0   _PieCtrlRegs
    00000d00   _PieVectTable
    00000e00   _PieVectTableCopy
    00001000   _DmaRegs
    00001700   _AnalogSysctrlRegs
    00004000   _FlashCtrlRegs
    00004300   _FlashEccRegs
    00004400   _M3PllRegs
    00004900   _RAMRegs
    00004a00   _RAMErrRegs
    00004e00   _CtoMIpcRegs
    00005000   _McbspaRegs
    00005100   _EPwm1Regs
    00005180   _EPwm2Regs
    00005200   _EPwm3Regs
    00005280   _EPwm4Regs
    00005300   _EPwm5Regs
    00005380   _EPwm6Regs
    00005400   _EPwm7Regs
    00005480   _EPwm8Regs
    00005500   _EPwm9Regs
    00005a00   _ECap1Regs
    00005a20   _ECap2Regs
    00005a40   _ECap3Regs
    00005a60   _ECap4Regs
    00005a80   _ECap5Regs
    00005aa0   _ECap6Regs
    00005b00   _EQep1Regs
    00005b40   _EQep2Regs
    00005b80   _EQep3Regs
    00005f80   _GpioCtrlRegs
    00005f80   _GpioG1CtrlRegs
    00005fc0   _GpioDataRegs
    00005fc0   _GpioG1DataRegs
    00005fe0   _GpioG1TripRegs
    00005fe0   _GpioTripRegs
    00006400   _Comp1Regs
    00006420   _Comp2Regs
    00006440   _Comp3Regs
    00006460   _Comp4Regs
    00006480   _Comp5Regs
    000064a0   _Comp6Regs
    00006f80   _GpioG2CtrlRegs
    00006fc0   _GpioG2DataRegs
    00007010   _SysCtrlRegs
    00007040   _SpiaRegs
    00007050   _SciaRegs
    00007060   _NmiIntruptRegs
    00007070   _XIntruptRegs
    00007100   _Adc1Regs
    00007100   _AdcRegs
    00007180   _Adc2Regs
    00007900   _I2caRegs
    00008000   _InitSysCtrl
    00008032   _InitPeripheralClocks
    0000808e   _CsmUnlock
    000080af   _EcslUnlock
    000080c6   _LockDevice
    000080ce   _GetEXEstatus
    000080e1   _CSMSecurityStatus
    000080ed   _ECSLSecurityStatus
    000080f9   _InitCpuTimers
    0000813a   _ConfigCpuTimer
    00008175   _c_int00
    000081bb   _InitPieCtrl
    000081df   _EnableInterrupts
    000081e8   _InitGpio
    0000820e   _InitPieVectTable
    0000822e   __args_main
    00008247   C$$EXIT
    00008247   _abort
    00008249   _exit
    00008260   _InitFlash
    00008285   _SetupFlash
    000082ae   _FlashGainPump
    000082bb   _FlashLeavePump
    000082c6   ___cinit__
    000082c6   cinit
    0000a000   _CpuTimer1
    0000a008   _CpuTimer2
    0000a010   _CpuTimer0
    0000a018   __unlock
    0000a01a   __lock
    0000a01c   __cleanup_ptr
    0000a01e   __dtors_ptr
    0013fff2   _FlashExeOnly
    0013fff4   _EcslPwl
    0013fff8   _CsmPwl
    ffffffff   .text
    ffffffff   ___binit__
    ffffffff   ___c_args__
    ffffffff   ___etext__
    ffffffff   ___pinit__
    ffffffff   ___text__
    ffffffff   binit
    ffffffff   etext
    ffffffff   pinit
    
    [201 symbols]
    

    /*
    //###########################################################################
    // FILE:    F28M35x_generic_C28_RAM.cmd
    // TITLE:   Linker Command File for generic Concerto examples that run out of 
    //          RAM.
    //          This ONLY includes all SARAM blocks on the Concerto device.
    //          This does not include flash or OTP.
    //          Keep in mind that L0 and L1 are protected by the code
    //          security module.
    //          What this means is in most cases you will want to move to
    //          another memory map file which has more memory defined.
    //###########################################################################
    // $TI Release: F28M35x Support Library v140 $
    // $Release Date: Tue Jul  3 09:38:11 CDT 2012 $
    //###########################################################################
    */
    
    /* ======================================================
    // In addition to this memory linker command file,
    // add the header linker command file directly to the project.
    // The header linker command file is required to link the
    // peripheral structures to the proper locations within
    // the memory map.
    // The header linker files are found in <base>\F28M35x_headers\cmd
    // For BIOS applications add:      F28M35x_Headers_BIOS.cmd
    // For nonBIOS applications add:   F28M35x_Headers_nonBIOS.cmd
    ========================================================= */
    
    /* Define the memory block start/length for the F28M35x
       PAGE 0 will be used to organize program sections
       PAGE 1 will be used to organize data sections
    
       Notes:
             Memory blocks on F28M35x are uniform (ie same
             physical memory) in both PAGE 0 and PAGE 1.
             That is the same memory region should not be
             defined for both PAGE 0 and PAGE 1.
             Doing so will result in corruption of program
             and/or data.
    
             Contiguous SARAM memory blocks can be combined
             if required to create a larger memory block.
    */
    
    MEMORY
    {
    PAGE 0 :
       /* BEGIN is used for the "boot to SARAM" bootloader mode   */
    
       BEGIN       : origin = 0x000000, length = 0x000040
       RAMM0       : origin = 0x0000B0, length = 0x0003B0     /* on-chip RAM block M0 */
       RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0, L1 */   
       RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L0, L1 */   
        
       RESET       : origin = 0x3FFFC0, length = 0x000002     /* Part of Boot ROM */
       FPUTABLES   : origin = 0x3FD258, length = 0x0006A0     /* FPU Tables in Boot ROM */
       IQTABLES    : origin = 0x3FD8F8, length = 0x000B50     /* IQ Math Tables in Boot ROM */
       IQTABLES2   : origin = 0x3FE448, length = 0x00008C     /* IQ Math Tables in Boot ROM */
       IQTABLES3   : origin = 0x3FE4D4, length = 0x0000AA     /* IQ Math Tables in Boot ROM */
    
       BOOTROM     : origin = 0x3FEDA8, length = 0x001200     /* Boot ROM */
    
    
    PAGE 1 :
    
       BOOT_RSVD   : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */
       RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
       RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
       RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
       CTOMRAM     : origin = 0x03F800, length = 0x000380     /* C28 to M3 Message RAM */
       MTOCRAM     : origin = 0x03FC00, length = 0x000380     /* M3 to C28 Message RAM */
    }
    
    
    SECTIONS
    {
       /* Setup for "boot to SARAM" mode:
          The codestart section (found in DSP28_CodeStartBranch.asm)
          re-directs execution to the start of user code.  */
       code_start		: > BEGIN,						 PAGE = 0
       .initMain		: > RAMM0,						 PAGE = 0
       ramfuncs         : >> RAMM0 | RAML0 | RAML1,      PAGE = 0
       .text            : >> RAMM0 | RAML0 | RAML1,      PAGE = 0
       .cinit           : >  RAMM0 | RAML0 | RAML1,      PAGE = 0
       .pinit           : >> RAMM0 | RAML0 | RAML1,      PAGE = 0
       .switch          : >> RAMM0 | RAML0 | RAML1,      PAGE = 0
       .reset           : >  RESET,                      PAGE = 0, TYPE = DSECT /* not used, */
    
       .stack           : >  RAMM1 | RAML2 | RAML3,      PAGE = 1
       .ebss            : >> RAML2 | RAML3 | RAMM1,      PAGE = 1
       .econst          : >> RAMM1 | RAML2 | RAML3,      PAGE = 1
       .esysmem         : >> RAMM1 | RAML2 | RAML3,      PAGE = 1
    
       IQmath           : >> RAMM0 | RAML0 | RAML1,      PAGE = 0
       IQmathTables     : >  IQTABLES,                   PAGE = 0, TYPE = NOLOAD
       
       /* The following section definitions are required when using the IPC API Drivers */ 
       GROUP : > CTOMRAM, PAGE = 1 
       {
           PUTBUFFER 
           PUTWRITEIDX 
           GETREADIDX 
       }
    
       GROUP : > MTOCRAM, PAGE = 1
       {
           GETBUFFER :    TYPE = DSECT
           GETWRITEIDX :  TYPE = DSECT
           PUTREADIDX :   TYPE = DSECT
       } 
       
       /* Allocate FPU math areas: */
       FPUmathTables    : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
    
       DMARAML2            : > RAML2,        PAGE = 1
       DMARAML3            : > RAML3,        PAGE = 1 
    
      /* Uncomment the section below if calling the IQNexp() or IQexp()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables2    : > IQTABLES2,  PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
    
       }
       */
       /* Uncomment the section below if calling the IQNasin() or IQasin()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables3    : > IQTABLES3,  PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
    
       }
       */
    
    }
    
    /*
    */
    
    
    

  • Mark,

    I think you should specify 0x0 as the entry point when you send the branch command to C28x.  I think you have below instruction at 0x00.

    code_start:
        LB _c_int00         ; Branch to start of boot.asm in RTS library
                            ; end codestart section

    This will initialize RTS and then branch to your main.

     

    Best Regards

    santosh