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c2000 as spi slave message synchronization

Genius 5910 points

I have 2 C2000 controllers that communicate with each other with SPI.

How do I know in the slave device that I received a complete message and not 2 halve messages? It looks like that the information of the rising edge of CS is lost in the hardware. So how do I know that I received the end of the message? 


  • evs,

    I am not sure what you mean "the information of the rising edge of CS is lost in the hardware" 

    This depends on your hardware connection. If you are using the CS (SPISTE) line, the slave will only receive data while the CS is active. If the master is toggling this appropriately for your communication link and assuming that the signals are not noisy, the slave will receive the data properly. One option on the slave side is to have a FIFO interrupt based on the number of data words transmitted. if you expect 4 words in a message, the slave could have an interrupt after 4 words.

    Alternately, you might add a handshake or error checking mechanism in your protocol to detect if the slave did not receive data properly. Something you could do is send a header plus data, and then dummy data from the master. The slave can detect a proper header, receive the data, and then during the dummy data transmitted from the master, the slave could provide and ACK to the master.

    The SPI protocol provides the hardware for data to move between devices, you must provide the payloads based on your application requirements.


  • Mark,

    To select a device with spi SPISTE is made low, data is send and SPISTE is made high again. if is high again that marks the end of the data transfer. So the data can be processed.
    in the C2000 there is no way of knowing that the end of the package is received. So I don't know if the data in the FIFO is two halve packages or one correct one. I noted synchronization problems.
    There is a way around to make a header bytes at the begin of the package. Only is it a high speed connection and wanted to uses spi so i don't need overhead. I'm limited by the size of the FIFO because I don't have time to wait for the SPI.

    So How do I know that the spi slave received a complete data block before the next one starts?

  • evs,

    This synchronization is something that the application must manage. You have said it correctly that the C2000 SPI does not have a way to detect if a complete transfer has been received. It only knows the number of words that it has received. If you are using F2837xD, F2837xS, or F2807x, the SPI does have access to the DMA. you can program the DMA to copy the data from the receive FIFO and generate an interrupt after a predefined length transfer is complete.

    Again, here, the issue is how to know if the first word is in fact the first word of a transfer, not the nth word. The application will need to do some sort of synchronization to detect this. You could do this periodically, or if you have tested and trust the application, you might only synchronize once at power up.

  • evs,

    Have these posts helped to answer your questions? If so, please provide your solution and verify an answer.


  • No, the only way to do it is at protocol level. So there is no gain in using SPI.
  • That would be correct. The SPI is only the physical layer. If you need additional synchronization, you would need to handle it at the protocol level as you said.
    I am going to close this post. If you find yourself with more questions, don't hesitate to create a new post.