TMS320F28377S - configure 50 MHz frequency

Hi Rajkumar,

Can you change the value TMR2INPCLKCTR to 0x200 (512) and see if it comes out of the while loop?

Regards,
Nirav

Hi Nirav,
Thanks for the update.
I have updated the TMR2INPCLKCTR to 0x200. Still it is not come out from the while loop.

Please review my configuration details:

file : F2837xS_Examples.h
#if CPU_FRQ_50MHZ
#define CPU_RATE 20.00L // for a 50MHz CPU clock speed (SYSCLKOUT)
#endif

file: F2837xS_SysCtrl.c
function : void InitFlash_Bank0(void)
#if CPU_FRQ_50MHZ
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x0; // flash wait state for 50 MHz
#endif

Please review the settings and provide your feedback.

Thanks,
Rajkumar

Hi Rajkumar,

Let me re-iterate the problem to confirm, when you run InitSysPLL by configuring SYSCLK=60MHz, you do not have any issues, but when you change SYSCLK=50MHz, you start seeing problems, where the code gets stuck in the while loop, is the understanding correct? If so, what configuration you use to configure SYSCLK=60MHz?

Regards,
Nirav

Hi Nirav,

Yes. the code gets stuck at "void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel)" function, when the controller is running at SYSCLK=50 MHz .

XTAL_OSC frequency is 20 MHz.

60 MHz configuration:

InitSysPll(XTAL_OSC,IMULT_12,FMULT_0,PLLCLK_BY_4);

InitAuxPll(XTAL_OSC,IMULT_12,FMULT_0,PLLCLK_BY_4);



file : F2837xS_Examples.h

#if CPU_FRQ_60MHZ

#define CPU_RATE 16.66L // for a 60MHz CPU clock speed (SYSCLKOUT)
#endif

Timer 2 clock counter:

#define TMR2INPCLKCTR 0x800

file: F2837xS_SysCtrl.c
function : void InitFlash_Bank0(void)
#if CPU_FRQ_60MHZ
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x01; // flash wait state for 60 MHz
#endif

Please review the configuration and provide your observations.

Thanks,

Rajkumar

Hi Rajkumar,

Ok, Can you try rwait=1 for 50MHz SYSCLK?

Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x1; // flash wait state for 50 MHz

Regards,
Nirav

Hi Nirav,
I changed the flash wait state to 1. Still, the issue didn't resolve.
I am facing same problem for 40 MHz and 55 MHz frequencies too.
How you derived the TMR2INPCLKCTR to 0x200 (512) value for SYSCLK=50 MHz?
Please provide the details.

Thanks,
Rajkumar

Hi Rajkumar,

I'm currently looking into this.

Regards,
Joseph

Hi Rajkumar,

It looks like the example code in the C200Ware has bug when you run the SYSCLK lower than 60MHz, hence you were seeing issue when you ran it at 50MHz. We will fix it in the next release. For now you can configure the SYSCLK at higher frequency i.e. SYSCLK=100MHz, and then divided it down to 50MHz outside InitSysPLL. For example:

InitSysPll(XTAL_OSC,IMULT_10,FMULT_0,PLLCLK_BY_2);
EALLOW;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = PLLCLK_BY_4;
EDIS;

Regards,
Nirav

Hi Nirav,

Thanks for the update.

I tried with the below configuration. Still, i am facing the same issue.

EALLOW;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = PLLCLK_BY_4;
EDIS;

Code gets stuck with below while loop. The lock bit is not not correctly. 

// Wait for the SYSPLL lock counter
//
while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1).

In the InitSysPll function, 

if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) &&
(imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) &&
(fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) &&
(divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV))
{

if the divsel value is same, it will return.

As per you suggestion, The system clock will configure every time due to divsel value.

The value of ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV is one always.  

whether this issue due to the software library or due to the hardware? please confirm.

Thanks,

Rajkumar 

Hi Rajkumar,

So when you configure SYSCLK=100MHz, the code gets stuck inside the InitSysPLL function, is that what you are observing? Did you configure the PLL with below configuration where SYSCLK=100MHz? 

InitSysPll(XTAL_OSC,IMULT_10,FMULT_0,PLLCLK_BY_2);

I am little confused because based on your previous message when you configured SYSCLK=60MHz the code worked. Can you share your project? Or send a snippet of your code highlighting the function where it gets stuck?

There is no issue as such with Hardware or Software library, but since you are trying to configure SYSCLK=50MHz which is lower than rated frequency of the device, there are some Hardware limitation which can be mitigated with Software  update.

Regards,

Nirav

Hi Nirav,
Thanks for your quick feedback. Please find the code snippet for the clock configuration.

InitSysPll(XTAL_OSC,IMULT_10,FMULT_0,PLLCLK_BY_2);
EALLOW;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = PLLCLK_BY_4;
EDIS;
InitAuxPll(XTAL_OSC,IMULT_10,FMULT_0,PLLCLK_BY_2);
EALLOW;
ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = PLLCLK_BY_4;
EDIS;


when i am running the code in flash, The code is getting struck with the below line.
function name : void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel)

while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) // stuck here.



Please provide the rated frequency of the device. It will help us to decide the clock frequency for our product.

Thanks,
Rajkumar