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TMS320F280049C: Options to restrict peripheral registers access

Gennadi Starobinski
Intellectual 420 points

Part Number: TMS320F280049C

Hi,

what options do I have to restrict access to peripheral registers?

For example:
1) CLA may use GPIO5, CPU not. However, the CPU must not change the configuration register of GPIO5 after initialization.
2) CPU configures and starts CLA. But after that CPU should can not change CLA configuration anymore.

I can also present similar examples for other periferals (PWM, DAC, ...).

Can I possibly use DCSM for this? Can DCSM ever protect the peripheral registers?

Thank you in advance

  • 0
    TI__Guru** 116131 points

    Hi,

    DCSM does not protect accesses to peripheral but we do have peripheral access protection feature which can be enable to do what you are looking for. Please refer section "3.14.18 PERIPH_AC_REGS Registers" and register definition for the same.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 420 points

    Hi.  Thanks for the answer.  If I first select CLA as master in the PERIPH_AC_REGS  register.  How can I make sure that CPU can not change it again later?

    Regards

  • 0 in reply to Gennadi Starobinski
    TI__Guru** 116131 points

    Hi,

    If your concern is with invalid (run away) CPU code changing the settings again then these registers have EALLOW protection and you can also disable the write to all access control register by setting "LOCK_AC_WR" bit to '1' in PERIPH_AC_LOCK register.

    Regards,

    Vivek Singh

     

  • 0 in reply to Vivek Singh
    Intellectual 420 points

    Hi,

    it is not a question of an invalid CPU code, but a way of preventing parts of the software from accessing certain registers. A kind of managing different permissions for hardware access. So I can do it with the "LOCK_AC_WR" bit. Can the CPU clear this bit later or only after a reset? I need a way to completely prevent the parts of the software from accessing certain configuration registers (up to reset).

  • 0 in reply to Gennadi Starobinski
    TI__Guru** 116131 points

    HI,

    Can the CPU clear this bit later or only after a reset? I need a way to completely prevent the parts of the software from accessing certain configuration registers (up to reset).

    If you look into the definition of this bit in TRM, the type is mentioned as "R/WSonce" which means it can be only "SET ONCE" after reset. After that it can not be changes till next reset.

    Regards,

    Vivek Singh