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TMS320F28388D: MDIO from EtherCAT

James Hendrix
Prodigy 20 points

Part Number: TMS320F28388D

Hello,

How does one access MDIO (PHY) from the EtherCAT subsystem? Documentation indicates it is possible, but I see no register descriptions or other method of access. I see assignment of GPIO pins (152/153) in example ESC code, but no usage. Trying to adapt Ethernet code failed.

Could someone kindly point out what I have missed? I have a need to modify PHY registers before bringing up EtherCAT PDI.

  • 0
    TI__Intellectual 1430 points

    Hi,

    As per the ESC hardware data sheet, access is only possible through the MII Management Interface registers. It also depends if PDI side MII access is enabled or not in the configuration. I will have one of my colleagues check that.

    Thanks,

  • 0 in reply to Ranjith Lohithakshan
    TI__Expert 4620 points

    Hi,

    MII management control is by default set only to the ECAT master. PDI has to claim access to MII management via the Ethercat IP register "MII Management PDI Access State (0x0517)" .

    This will open the MII management access to PDI. Once this is enabled, the PDI can access the Phy registers via the "MII Management Control" & "PHY Address" registers

    Regards,
    Praveen

  • 0 in reply to Praveen Kumar Ravichandran
    Prodigy 20 points

    Thank you for the explanation, but I am still a bit confused.

    I have conflicting figures in the 28388D docs. One shows MDIO going into ESCSS and another shows it going to the EtherCAT IP core. Documentation also suggests I need to use ESCSS_MISC_CONFIG.PHY_ADDR[4:0] to set PHY address.

    But all I need to do is access registers in the IP core via PDI? Is that correct?

  • 0 in reply to James Hendrix
    TI__Expert 4620 points

    Hi,

    As shown in the figure 31-8, the ECSS is the subsystem which has the Ethercat IP core implemented inside, hence you might see the MDIO interface shown interchangeably between ESCSS and IP core.

    For configuring phy registers from the F2838x core, you need to configure the "MII Management Interface" registers inside the Ethercat IP core via the PDI interface

    The ESCSS_MISC_CONFIG.PHY_ADDR[4:0] is used to program the optional PHY address offset as given in the Bechoff ESC Hardware datasheet under "PHY Addressing/PHY Address Offset" section.

    Regards,
    Praveen

  • +1 in reply to Praveen Kumar Ravichandran
    Prodigy 20 points

    FWIW, from my perspective, the diagrams absolutely matter:

    One has registers I can directly access and causes confusion when there are no registers pertaining to MDIO.

    The other does not confuse as much, but neglects to mention PDI is required. I should have realized this, but I suspect most will not as well.

    A small paragraph explaining access and enabling should eliminate further questions.

  • 0 in reply to James Hendrix
    TI__Expert 4620 points

    Sure. I will pass on this feedback to our technical documentation team.

    Regards,
    Praveen