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TMS320F280049: TCA9539 lost stop bit

Part Number: TMS320F280049
Other Parts Discussed in Thread: TCA9539, C2000WARE, AWR1843BOOST

Dear team:

One of my customers uses I2C module of F280049 to communicate with TCA9539 chip.

When the baud rate is set to 100kHz, observe the waveform and find that the chip will have no data/clock after a period of normal communication. If the baud rate is set to 50/10kHz, the communication will always be normal and the waveform will be correct.

It is observed that after TCA9539 sends the IO information, the I2C chip of 280049 should first generate a NACK bit, and then generate a STOP bit to end the reading process. When something went wrong, 280049 did not generate the STOP bit after sending the NACK bit, but instead generated the RESTART bit, which resulted in a timing mismatch with TCA9539.

  • Green,

    I2C module in F280049 will not generate START condition / repeated START condition unless I2CMDR.STT = 1 bit is set.

    Based on the failure description, I get a feeling that customer isn't waiting for previous read transaction to complete. When polling method is used, you need to wait for STOP condition to be generated before you set I2CMDR.STT = 1.

    In your code, before you set I2CMDR.STT = 1 is set make sure to wait for I2CMDR.STP is cleared. In short, never set I2CMDR.STT before making sure I2CMDR.STP is cleared.

    Regards,

    Manoj

  • Hi, Manoj

    I am the customer, I don't have the authority to ask a question in the forum before the last weekend because the E2E upgrade, so thanks for Green's helping.

    I am confused about the question, I read the register value of I2CMDR.STP when the issue occured, it was 1.

    So what reason will dirve the I2C module not send a STOP on data pin?

    I use the polling method to read I2C, the code is derived from example in C2000ware。

    Uint16 I2CwriteData(volatile struct I2CMsg *msg)
    {
        Uint16 i;
    
        //
        // Wait until the STP bit is cleared from any previous master
        // communication. Clearing of this bit by the module is delayed until after
        // the SCD bit is set. If this bit is not checked prior to initiating a new
        // message, the I2C could get confused.
        //
        if(I2C_getStopConditionStatus(I2CA_BASE))
        {
            return(ERROR_STOP_NOT_READY);
        }
    
        //
        // Setup slave address
        //
        I2C_setSlaveAddress(I2CA_BASE, SLAVE_ADDRESS);
    
        //
        // Check if bus busy
        //
        if(I2C_isBusBusy(I2CA_BASE))
        {
            return(ERROR_BUS_BUSY);
        }
    
        //
        // Setup number of bytes to send msgBuffer and address
        //
        I2C_setDataCount(I2CA_BASE, (msg->numBytes + 1));
    
        //
        // Setup data to send
        //
        I2C_putData(I2CA_BASE, msg->RegAddr);
    
        for (i = 0; i < msg->numBytes; i++)
        {
            I2C_putData(I2CA_BASE, msg->msgBuffer[i]);
        }
    
        //
        // Send start as master transmitter
        //
        I2C_setConfig(I2CA_BASE, I2C_MASTER_SEND_MODE);
        I2C_sendStartCondition(I2CA_BASE);
        I2C_sendStopCondition(I2CA_BASE);
    
        return(I2C_SUCCESS);
    }

    Additionally, I find some similar feedback in E2E "AWR1843BOOST: I2C can not generate STOP condition"

    Hope for your support!

  • Tao,

    If you have used the above I2CWriteData function, it would return ERROR_STOP_NOT_READY error if I2CMDR.STP bit is set to 1.

    Can you please check the new I2C EEPROM polling example in below path. This should most likely resolve your issue.

    C2000Ware\driverlib\f28004x\examples\i2c\i2c_ex4_eeprom_polling

    Regards,

    Manoj

  • Tao,

    Did you try the below example? Did it work for you? Can I close this thread?

    C2000Ware\driverlib\f28004x\examples\i2c\i2c_ex4_eeprom_polling

    Regards,

    Manoj