TMS320F28234-Q1: Flash Related Issues

Part Number: TMS320F28234-Q1
Other Parts Discussed in Thread: TMS320F28234

Heloo,

I am using TMS320F28234 , doing a sensorless vector control. While the program is working from RAM, my control loops are perfect.  When I am flashing the program ripple in current  are more and hence the current harmonics.  I am using .asm files provided by TI for changing RAM to flash.  The flash program after power up are changed to RAM using API's. 

I have two observations , would like to know the reasons

1) The control loop takes 7-8us more compared to RAM. Even-though the program runs at RAM. Would like to know the reason for the same ??

2) What may cause higher current ripples while Flashing. Is there any issues in ADC while running form FLASH.

Regards

Manoj.R 

  • Manoj,

    1) Flash memory is not as fast as RAM.  It takes additional cycles to fetch/read content from flash.  These additional cycles are called as wait-states.  You might have used flash initialization routine in your application.  In that, you can see that the wait-states are configured based on your application's operating frequency.

    We suggest to copy any time critical ISRs or control loops to RAM to achieve the required performance.

    2) When you say flashing, do you mean flash erase/program operations?  Or do you mean execution from flash?  Datasheet should have a power consumption summary for active flash (execution and also for erase/program).  Did you check the datasheet?

    Our analog expert will address your ADC question.

    Thanks and regards,
    Vamsi

  • Manoj,

    To add to Vamsi's reply there's no known cross talk between code execution from flash and ADC sampling.

    Best,

    Matthew

  • Hi Vamsi,

    Thanks for the response. We are using SectionCopy.asm provided by TI. How will you ensure the time critical functions are executed from RAM.

    Regards

    Manoj.R

  • Hi Vamsi,

    Thanks for the response. We are using SectionCopy.asm provided by TI. How will you ensure the time critical functions are executed from RAM.

    Regards

    Manoj.R

  • Manoj,

    Do you mean to say that you are copying your entire application to RAM using sectioncopy.asm discussed in https://www.ti.com/lit/pdf/spraau8?

    If yes, it means that you are executing from RAM already - do you agree?

    Can you do step execution and see whether your code (control loop) is executing from RAM or not (look at the disassembly window)?  

    Thanks and regards,
    Vamsi

  • Dear Vamsi,

    We have copied our entire code to RAM. We have followed the same procedure as illustrated in the document. Our control loop also works from RAM. What may cause the difference in control loop performance  when we moved to Flash ??

    Regards

    Manoj.R

  • Manoj,

    Is it accessing any data from flash?  

    If yes, you may want to move that as well to RAM.

    Thanks and regards,
    Vamsi

  • Hi Vamsi,

    While analyzing the disassembly code, we are able to see the breakpoints in control loop is not hitting in defined RAM location , where as the same function in FLASH in been hit. 

    Could you pls share some reference, (SectionCopy.asm) to ensure the control loop is executed from RAM..

    Regards

    Manoj.R

  • Manoj,

    That's what I thought and hence asked.  I think the copy to RAM is not correctly implemented in the application.

    Before we go further on this, I have a question for you:  What is the reason for you to copy the entire application to RAM?  Is it not enough to copy only the time critical code and any other initialization routines (like flash init)?

    Thanks and regards,

    Vamsi

  • Hi Vamshi,

    We thought of having the best speed , hence copying the entire code to RAM. 

    We were using SectionCopy.asm , Code_StartBranch.asm and FLASH.cmd provided by TI long back. And the code was working perfectly in Flash.

    We have changed the software architecture recently to optimize the control loop performance. We have two ISR, time critical  routines. We shall also try to move only these two ISR's in RAM. 

    We have defined Flash and RAM locations in Flash.cmd and further having these lines.

    INTERRUPT : LOAD = INTERRUPT_FLASH, PAGE = 0 /* can be ROM */
    RUN = INTERRUPT_RAM, PAGE = 0 /* must be CSM secured RAM */
    TZ_INTERRUPT : LOAD =TZ_INTERRUPT_FLASH, PAGE = 0 /* can be ROM */
    RUN = TZ_INTERRUPT_RAM, PAGE = 0 /* must be CSM secured RAM */
    TMR_INTER : LOAD = TMR_INTER_FLASH, PAGE = 0 /* can be ROM */
    RUN = TMR_INTER_RAM, PAGE = 0 /* must be CSM secured RAM */

    And used 

    #pragma CODE_SECTION (EPWM_INT_ISR,"INTERRUPT")
    #pragma CODE_SECTION (EPWM_TZ_INT_ISR,"TZ_INTERRUPT")
    #pragma CODE_SECTION (TIMER_ONE_ISR,"TMR_INTER")

    Hence we thought the code loaded from flash further executed from RAM. 

    And copied entire code to RAM using sectioncopy.asm

    MOVL XAR5,#_const_size ; Store Section Size in XAR5
    MOVL ACC,@XAR5 ; Move Section Size to ACC
    MOVL XAR6,#_const_loadstart ; Store Load Starting Address in XAR6
    MOVL XAR7,#_const_runstart ; Store Run Address in XAR7
    LCR copy ; Branch to Copy

    MOVL XAR5,#_econst_size ; Store Section Size in XAR5
    MOVL ACC,@XAR5 ; Move Section Size to ACC
    MOVL XAR6,#_econst_loadstart ; Store Load Starting Address in XAR6
    MOVL XAR7,#_econst_runstart ; Store Run Address in XAR7
    LCR copy ; Branch to Copy

    MOVL XAR5,#_pinit_size ; Store Section Size in XAR5
    MOVL ACC,@XAR5 ; Move Section Size to ACC
    MOVL XAR6,#_pinit_loadstart ; Store Load Starting Address in XAR6
    MOVL XAR7,#_pinit_runstart ; Store Run Address in XAR7
    LCR copy ; Branch to Copy

    MOVL XAR5,#_switch_size ; Store Section Size in XAR5
    MOVL ACC,@XAR5 ; Move Section Size to ACC
    MOVL XAR6,#_switch_loadstart ; Store Load Starting Address in XAR6
    MOVL XAR7,#_switch_runstart ; Store Run Address in XAR7
    LCR copy ; Branch to Copy

    MOVL XAR5,#_text_size ; Store Section Size in XAR5
    MOVL ACC,@XAR5 ; Move Section Size to ACC
    MOVL XAR6,#_text_loadstart ; Store Load Starting Address in XAR6
    MOVL XAR7,#_text_runstart ; Store Run Address in XAR7
    LCR copy ; Branch to Copy

    MOVL XAR5,#_cinit_size ; Store Section Size in XAR5
    MOVL ACC,@XAR5 ; Move Section Size to ACC
    MOVL XAR6,#_cinit_loadstart ; Store Load Starting Address in XAR6
    MOVL XAR7,#_cinit_runstart ; Store Run Address in XAR7
    LCR copy ; Branch to Copy

    MOVL XAR5,#_RamFuncs_size ; Store Section Size in XAR5
    MOVL ACC,@XAR5 ; Move Section Size to ACC
    MOVL XAR6,#_RamFuncs_loadstart ; Store Load Starting Address in XAR6
    MOVL XAR7,#_RamFuncs_runstart ; Store Run Address in XAR7
    LCR copy ; Branch to Copy

    MOVL XAR5,#_ramFuncs_size ; Store Section Size in XAR5
    MOVL ACC,@XAR5 ; Move Section Size to ACC
    MOVL XAR6,#_ramFuncs_loadstart ; Store Load Starting Address in XAR6
    MOVL XAR7,#_ramFuncs_runstart ; Store Run Address in XAR7
    LCR copy ; Branch to Copy

    LB _c_int00

    Could you pls suggest us how shall we proceed further to get the best performance for our control loop.

    Regards

    Manoj.R

  • Hi Vamsi,

    We thought of having the best performance, hence moved the entire code to RAM.

    We were using SectionCopy.asm , CodeStartBranch.asm and Flash.cmd from long back and were working perfectly.

    We have recently changed our software architecture so as to get the best control performance. We have two time critical ISR we shall plan to move only these two too in RAM.

    We have defined Flash and RAM locations for our interrupts and using these line of codes.

    INTERRUPT : LOAD = INTERRUPT_FLASH, PAGE = 0 /* can be ROM */
    RUN = INTERRUPT_RAM, PAGE = 0 /* must be CSM secured RAM */
    TZ_INTERRUPT : LOAD =TZ_INTERRUPT_FLASH, PAGE = 0 /* can be ROM */
    RUN = TZ_INTERRUPT_RAM, PAGE = 0 /* must be CSM secured RAM */
    TMR_INTER : LOAD = TMR_INTER_FLASH, PAGE = 0 /* can be ROM */
    RUN = TMR_INTER_RAM, PAGE = 0 /* must be CSM secured RAM */

    #pragma CODE_SECTION (EPWM_INT_ISR,"INTERRUPT")
    #pragma CODE_SECTION (EPWM_TZ_INT_ISR,"TZ_INTERRUPT")
    #pragma CODE_SECTION (TIMER_ONE_ISR,"TMR_INTER")

    Hence we thought ISR loaded initially from flash and running from RAM. 

    Could you pls suggest us the way to have the best control performance.

    Regards

    Manoj.R

  • Manoj,

    Ok, glad to know that you decided to copy only a couple of critical ISRs to RAM instead of the entire application.

    Regarding the question that you asked, please take a look at section 4.4 Initializing the Flash Control Registers (DSP/BIOS and non-DSP/BIOS projects) in https://www.ti.com/lit/pdf/spra958. You can follow similar process for your time critical ISRs.

    In general, it would be a good idea to review the above guide.

    Thanks and regards,

    Vamsi

  • Manoj,

    Did it help?  Can I close this post?

    Thanks and regards,
    Vamsi

  • Hi Vamsi,

    I have verified in Controller. Have to verify with actual hardware . 

    Regards

    Manoj.R

  • Manoj,

    Ok, please let me know once you verify.

    Thanks and regards,
    Vamsi