TMS320F28379D: The 100% ePWM duty cycle

Marlyn,

Do you mean for the EPWM type greater than 0, we can use up-down count and get 0% duty cycle by setting CMPA = PRD and obtain 100% duty cycle if CMPA = 0?

If this is the case, please refer to chapter 15.6.5 Waveforms for Common Configurations in TRM, I also get same descriptions in F28004x, F2807x and F2838x TRMs. Should we modify the descriptions of this chapter in the TRMs please?

Regards,

Luke

Hi Luke, 

Yes, this post has more information on the matter: https://e2e.ti.com/support/microcontrollers/c2000/f/c2000-microcontrollers-forum/646249/tms320f28075-type-4-epwm-to-generate-full-range-0-100-duty-cycle-waveform-w-o-isr-intervention

I agree, the documentation should be changed. I'll file a ticket so we get this changed for the next TRM revision.

Best Regards,

Marlyn

Hi Marlyn

For type-0 PWM, the actual duty cycle will be always one cycle delay if we don’t implement the workarounds. For example, we cannot get 100% duty with CMPA = 0 in the first 100% cycle with workaround, but we can get this in the second 100% cycle, is this correct?

For type-4 PWM, we can get 100% duty in first cycle when CMPA = 0 without any workaround. In the thread, Cody suggested we should apply the workaround when CMPA switch from 0 to a non-zero value, what will happen if we don’t use this workaround?

Regards,

Luke

Hi Luke,

Yes, that is correct.

If the workaround is not applied then a pulse is missed, the way to correct this is to add the workaround.

Best Regards,

Marlyn

Hi Marlyn,

I understand the reason Type-4 PWM doesn't need workaround and is able to get 100% duty when CMPA = 0.

But I don't know the details why do we need workaround when CMPA switch from 0 to a non-zero value so that we are sure no pulses is missed? Could you please advise more about this?

Regards,

Luke

Hi Luke,

I don't have the exact details for this. Please allow me some time to get those details for you. I'll reply back once I obtain more information internally.

Best Regards,

Marlyn

Hi Luke,

Yes, if the workaround is not applied then you will see a missing pulse because the output will not be cleared otherwise (this will cause an extended high period and hence, missing pulse)

Best Regards,

Marlyn

Marlyn,

Because Type-4 PWM shadow load occurs before CMPA is compared to TBCTR, we won't miss pulse when CMPA switch from a non-zero value to 0.

I would like to understand the reason we miss pulse when CMPA switch from 0 to a non-zero value if the workaround is not applied, is this due to any timing sequence of register data loading?

Regards,

Luke