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TMS320F28379D: EMIF

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE, LAUNCHXL-F28379D, TMDSCNCD28379D

Hi,

I am trying to interface an external ASRAM (ISSI IS61WV25616EDBLL-10TL) with my TMS320F28379D. I have a daughterboard built according to TI specs. However when I run the emif_ex1_16bit_asram.c there is no data write and the errCountGlobal = 4. Are there any tests I can run to understand what is wrong? Thank you.

  • I have a daughterboard built according to TI specs.

    Can you elaborate on which TI specs you are referring to?

    However when I run the emif_ex1_16bit_asram.c there is no data write and the errCountGlobal = 4.

    Did you customize the EMIF delays to match the timing requirements for your ASRAM? The C2000-EMIF_ConfigurationTool.xlsx is helpful for that: ~\C2000Ware_XXXX\boards\TIDesigns\F28379D_EMIF_DC\

    Are you able to interact with any EMIF locations using the Memory Browser after configuring EMIF?  If not, you may need to observe some EMIF control signals using a scope to see if there are signal integrity issues.

    Are there any tests I can run to understand what is wrong?

    Are you using the design that is referenced by the EMIF appnote?  (~\C2000Ware_XXXX\boards\TIDesigns\F28379D_EMIF_DC\)

    If so, the appropriate examples would be the emif_dc_* examples located here:  ~\C2000Ware_XXXX\device_support\f2837xd\examples\cpu1\

  • Hi,

    I am using the design that is referenced by the EMIF appnote  (~\C2000Ware_XXXX\boards\TIDesigns\F28379D_EMIF_DC\). I am running the 

    emif_ex1_16bit_asram.c code by using the default  delays.

    tparam.rSetup = 0;
    tparam.rStrobe = 3;
    tparam.rHold = 0;
    tparam.turnArnd = 0;
    tparam.wSetup = 0;
    tparam.wStrobe = 1;
    tparam.wHold = 0;

    Could you let me know what the values of the dealy should be for ISSI IS61WV25616EDBLL-10TL? Thank you.

  • I am using the design that is referenced by the EMIF appnote

    Please try the emif_dc_* examples. They were developed to run on the EMIF daughtercard design.

    Please also verify that the software project and hardware are configured as recommended in the Guidelines for Evaluation Boards table from the appnote.

    Could you let me know what the values of the dealy should be for ISSI IS61WV25616EDBLL-10TL?

    The emif_dc_* examples are pre-populated with timings for the components used in the reference design, which includes this ASRAM.

  • Hi,

    The emif_dc_cla code works perfectly with the ASRAM. I used the same timing configurations from emif_dc_cla code in the  emif_ex1_16bit_asram.c.

    However, the data written onto the ASRAM gets rewritten to zero.

  • Snambiar,

    The emif_dc_cla example takes care of hardware features that are specific to the emif daughtercard design -- for example, the GPIO-controlled paging, and cross-EVM support for both LAUNCHXL-F28379D and TMDSCNCD28379D.

    The emif_ex1_16bit_asram example will need to accommodate the variations (noted in the Hardware Differences Between Evaluation Boards section of the appnote) that apply to your run environment.

    -Tommy

  • Hi,

    I am trying a simple write to the 16 bit ASRAM on the Daughter card. I got the emif_dc.c and emif_dc.h files into the emif_ex1_16bit_asram.c.

    The code is as follows:

    ###########################################################################

    //
    // Included Files
    //
    #include "F28x_Project.h"
    #include "emif_dc.h"

    //
    // Constants
    //
    #define EMIF_NUM EMIF_DC_F2837X_CONTROLCARD_EMIF_NUM
    //#define BUFFER_WORDS 256

    //
    // Global Variabls
    //

    //#pragma DATA_SECTION(dstBuffer, ".em2_cs2");
    #define ASRAM_CS2_START_ADDR 0x100000
    #define ASRAM_CS2_SIZE 0x8000


    //Function Prototype
    char
    mem_read_write(Uint32 start_addr, Uint32 mem_size);
    //extern void setup_emif1_pinmux_async_16bit(Uint16);


    //
    // Main
    //
    void main(void)
    {


    //
    // Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    //
    InitSysCtrl();

    DINT;

    //
    // Initialize the PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.
    // This function is found in the F2837xD_PieCtrl.c file.
    //
    InitPieCtrl();

    //
    // Disable CPU interrupts and clear all CPU interrupt flags:
    //
    EALLOW;
    IER = 0x0000;
    IFR = 0x0000;
    EDIS;

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // GService Routines (ISR).
    // This will populate the entire table, even if the interrupt
    // is not used in this example. This is useful for debug purposes.w
    // The shell ISR routines are found in F2837xD_DefaultIsr.c.
    // This function is found in F2837xD_PieVect.c.
    //
    InitPieVectTable();

    //
    // Initialize EMIF module for use with daughtercard
    //
    EALLOW;
    EMIF_DC_setupPinmux(EMIF_NUM, GPIO_MUX_CPU1);
    EMIF_DC_initModule(EMIF_NUM);
    EMIF_DC_initCS0(EMIF_NUM);
    EMIF_DC_initCS2(EMIF_NUM, EMIF_DC_ASRAM);

    EDIS;


    char c = mem_read_write(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE);
    // setup_emif1_pinmux_async_16bit(1);


    }

    char
    mem_read_write(Uint32 start_addr, Uint32 mem_size)
    {

    unsigned long mem_wds;
    long *XMEM_ps;
    unsigned int i;
    unsigned int j;

    //
    //Write data
    //
    XMEM_ps = (long *)start_addr;

    //
    //Fill memory
    //
    mem_wds = 0x12340000;
    for (i=0; i < mem_size; i++)
    {


    *XMEM_ps++ = mem_wds;
    mem_wds += 0x00001000;
    for (j = 0; j < 1000; j++) {};

    }

    return(0);
    }

    If I switch to EMIF1 the data is written in block but is reset to zero. The code doesn't work with EMIF2. I have spare Daughter Cards which I can ship over in case you want to try the code.

  • Snambiar,

    I suspect that there are still differences at play. For example, if you refer to the daughtercard schematics, you will see that only 14-bits (A[13:0]) of the memory address pins are mapped to EMIF-controlled address signals. As such, access to memory beyond offset 0x4000 will require GPIO-based paging.

    Software-wise, the emif_ex1_16bit_asram.c example was written to use 32-bit operations, so the memory word counters are 32-bit words, not 16-bit.

    -Tommy

  • Hi,

    Thank you for your inputs. I need a way to write to the ASRAM on the Daughter Card without using the CLA. Please let me know what changes need to be made in the code for this to work. Thank you. 

  • Hi,

    If I switch to EMIF1 the data is written in block but is reset to zero.

    When EMIF data becomes 0, did you check the EMIF configuration ? If for some reason device gets reset then EMIF data will show 0x0 because all the configuration is lost.

    You mentioned that you are able to run CLA code properly. If yes then you should be able to use the same code for CPU. In fact the EMIF configuration will be part of CPU code only. Just add the RD/WR code and that should work. 

    I am finding little bit difficult to understand the issue in this case. 

    Regards,

    Vivek Singh

  • Hi,

    Please let me know any other findings or query you have on this topic.

    Regards,

    Vivek Singh

  • Hi,

     I used the emif_dc.c and emif_dc.h files and wrote a simple write operation but that keeps going back to zero. Are there any tests I can run to check if it is being reset? 

  • You can just have a breakpoint on reset entry point in ROM and if there is reset then CPU will halt at this breakpoint. Once CPU halts, you can check the value in RESC (reset cause) register to know what caused the reset. 

    Regards,

    Vivek Singh

  • Hi,

    How do I set up a  breakpoint on reset entry point in ROM?

  • Hi,

    After connecting vis CCS, issue debug reset and check the PC value or open the disassembly view in CCS and put the breakpoint where PC is pointing.

    Regards,

    Vivek Singh