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TMS320F28375D: Phenomenon that the waveform configured in the DB submodule has a delay of 10ns more than the set value.

Conor
Mastermind 8120 points
Part Number: TMS320F28375D

Hi,

I have a question about the DB submodule of PWM.

The dead band operation mode is set to active / high complement.

When I checked the waveform with an oscilloscope, both the rising and falling edge delays were 10ns longer than the setting.

Is this a specification?

The settings related to the DB submodule are as follows.


- Epwm1Regs.DBCTL.bit.OUT_MODE = 0x3;

- Epwm1Regs.DBCTL.bit.POLSEL = 0x2;

- Epwm1Regs.DBCTL.bit.IN_MODE = 0x0;

- Epwm1Regs.DBCTL.bit.OUTSWAP = 0x0;

- Epwm1Regs.DBCTL.bit.DEDB_MODE = 0x0;

- Epwm1Regs.DBCTL.bit.HALFCYCLE = 0x0;

 

Thanks,

Koki

  • 0
    TI__Mastermind 22810 points

    Hi Koki,

    Without including the rising and falling edge delays is the output width as expected? 

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Mastermind 8120 points

    Hi, Marlyn

     

    Marlyn Rosales Castaneda20 said:
    Without including the rising and falling edge delays is the output width as expected? 

    Yes, the output width without including the rising and falling edge delays is as set.

    The confirmation method is to check whether the width from the fall of gate output B to the fall of gate output A matches the ON width of outA.

     

    Thanks,

    Koki

  • 0 in reply to Conor
    TI__Mastermind 22810 points

    Hi Koki,

    Your settings above are correct. What is the value of your delay in comparison to your duty cycle (ON time and OFF time)?

    If you could please include the rest of your initialization code that would be helpful.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Mastermind 8120 points
    Marlyn Rosales Castaneda20 said:
    Your settings above are correct. What is the value of your delay in comparison to your duty cycle (ON time and OFF time)?

    　

    TBPRD =0x53.55 , CMPA = 0x29.B5 , CMPB = 0x3F.5A.

    Therefore, the ON time is 0x3D.9B (about 616ns) and the OFF time is 0x15.BA (about 217ns).

    The delay time is 50ns since the setting value for both DBRED and DBFED = 0x5.

    　

    　

    　

    Marlyn Rosales Castaneda20 said:
    If you could please include the rest of your initialization code that would be helpful.

    　

    The code for the initialization part of the PWM is attached.

    　

    PWM_initialize.c 
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Up-down counter mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; // EPWMxSYNCL input signal / TBPHS to TBCTR with SWFSYNC
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // use shadow register for TBPRD
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // use EPWMxSYNCI/SWFSYNC for sync output
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // /1
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // /1
EPwm1Regs.TBCTL.bit.FREE_SOFT = 11; // free run
EPwm1Regs.TBPRD = 53; // 
EPwm1Regs.TBPRDHR = 55; // 
EPwm1Regs.TBCTR = 0x0000; // Clear the counter
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // Load from shadow when CTR = Zero/ CTR = PRD
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // Read from shadow when CTR = Zero/ CTR = PRD
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // use shadow register for CMPA
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // use shadow register for CMPB
EPwm1Regs.CMPCTL2.bit.LOADCMODE = CC_CTR_ZERO_PRD; // Load on CTR = Zero/ CTR = PRD
EPwm1Regs.CMPCTL2.bit.SHDWCMODE = CC_SHADOW; // use shadow register for CMPC
EPwm1Regs.CMPA.all = 0; // initialize CMPA
EPwm1Regs.CMPB.all = 0; // initialize CMPB
EPwm1Regs.CMPC = TB_CMPC; // initialize CMPC (ensure EPWM updateable time)
EPwm1Regs.AQCTL.bit.LDAQAMODE = AQ_CTR_ZERO; // read from shadow when CTR = Zero
EPwm1Regs.AQCTL.bit.SHDWAQAMODE = AQ_SHADOW; // use shadow register for Action Qualifier A
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // initially 0
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; // Both edges are controlled by MEP
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; // controlled by CMPAHR/CMPBHR register.
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // Read from shadow when CTR = ZERO or CTR = PRD.
EPwm1Regs.HRCNFG.bit.EDGMODEB = HR_BEP; // Both edges are controlled by MEP.
EPwm1Regs.HRCNFG.bit.CTLMODEB = HR_CMP; // controlled by CMPAHR/CMPBHR register.
EPwm1Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD; // Read from shadow when CTR = ZERO or CTR = PRD.
EPwm1Regs.HRCNFG.bit.AUTOCONV = HR_AUTO_EN; // Use Automatic HRMSTEP scaling
EPwm1Regs.HRPWR.bit.CALPWRON = HR_ENABLE; // Use MEP Calibration Power.
EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = HR_ENABLE; // synchronize TBPHSHR with SYNCIN,TBCTL[SWFSYNC] or digital comparator synchronization event
EPwm1Regs.HRPCTL.bit.HRPE = HR_ENABLE; // use high resolution period.
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // use both RED and FED
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // use Active high complement
POLSEL = DB_ACTV_HIC; // use active high complementation EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; // use EPWMxA In for both RED and FED
EPwm1Regs.DBCTL.bit.OUTSWAP = DB_OUT_AABB; // Do not swap OutA and OutB
EPwm1Regs.DBCTL.bit.DEDB_MODE = DEDB_RAFB; // RE applies to InA only, FE applies to InB only
EPwm1Regs.DBCTL.bit.HALFCYCLE = DB_FULL_CYC; // use full cycle clock
EPwm1Regs.DBRED.bit.DBRED = 5; // Set the rise dead time (50ns)
EPwm1Regs.DBFED.bit.DBFED = 5; // set the dead time of falling edge (50ns)
EPwm1Regs.TZCTL.bit.DCAEVT1 = 2; // force EPWM1A to output LOW when AEVT1 occurs
EPwm1Regs.TZCTL.bit.DCBEVT1 = 2; // force LOW output of EPWM1B when AEVT1 occurs
EPwm1Regs.TZEINT.bit.DCAEVT1 = 0; // Disable the Digital Comparator Output A Event interrupt
EPwm1Regs.TZEINT.bit.DCBEVT1 = 0; // Disable Digital Comparator Output B Event interrupt
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 1; // Condition for generating AEVT1: DCAH = Low, DCAL = don't care
EPwm1Regs.TZDCSEL.bit.DCBEVT1 = 1; // Condition of BEVT1 occurrence: DCBH = Low, DCBL = don't care
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0; // Select TZ1 as the signal source for DCAH
EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0; // select TZ1 as the signal source for DCBH
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; // source is asynchronous signal
EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 0; // do not use filter
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // event issued when TBCTR = 0
EPwm1Regs.ETSEL.bit.INTEN = ET_INT_EN; // use EPWMx_INT
EPwm1Regs.ETPS.bit.INTPRD = ET_CNT_FIRST; // interrupt on one event occurrence

    Thanks,

    Koki

  • 0 in reply to Conor
    TI__Mastermind 22810 points

    Hi Koki,

    Thank you for sharing your initialization code. If you use half cycle clocking and modify your RED/FED delay values accordingly so you still see the same issue?

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Mastermind 8120 points

    Hi, Marlyn

    Is it correct to understand that the frequency of EPWMCLK should be halved and the RED / FED delay values should be doubled?

    Thansk,

    Koki

  • 0 in reply to Conor
    TI__Mastermind 22810 points

    Hi Koki,

    By half cycle clocking I meant setting the HALFCYCLE bit of the DBCTL register. Whenever this bit is set the dead-band counters are clocked at TBCLK*2 so FED becomes DBFED × TTBCLK/2 and RED becomes equal to DBRED × TTBCLK/2

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Mastermind 8120 points

    Hi, 

    The time was measured with HALFCYCLE enabled.

    When RED / FED was set to 3 or higher, the time was almost as set. (Although it is not always as set and there are times when it is slippery, I think this is the functional limit.)


    If it is less than 3, it did not look like the set value, but it seems that there is no problem because the actual setting is 5 or more.


    Please confirm the above.

    Thanks,

    Koki

  • 0 in reply to Conor
    TI__Mastermind 22810 points

    Hi Koki,

    You mentioned that your actual setting is 5 or more... are you changing the delay values throughout your program? Something that could be useful for you to try is to enable shadow loading for the RED/FED values so that they are applied at a known point within your EPWM cycle.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    TI__Guru 51940 points

    I dont think there is limitation on RED/FED having to be larger than 3.

    Nima