C2000 microcontrollers forum - Recent Threads

RE: SYSCONFIG: SYSCONFIG fails to switch device

Kita Li — Fri, 08 May 2026 05:24:05 GMT

Hi Ki,

thanks for update. When will the sysconfig v1.28 released?

Best Regards

Kita

SYSCONFIG: SYSCONFIG fails to switch device

Kita Li — Wed, 06 May 2026 13:14:18 GMT

Part Number: SYSCONFIG

Hi experts,

My customer is developing F29H85 with ccs 20.5. They found that when the computer has no internet, the device type can't be changed. Once they click "switch" in device interface, the following error will be shown.

I can also reproduce this when my computer is offline. Once the computer is online, then this error will disappear.

I want to know the reason on that and want to know how solve it ASAP, thanks

Best Regards

TMS320F28P650DK: ECAP Signal Monitoring

Haobo Zhang — Thu, 30 Apr 2026 22:56:26 GMT

Part Number: TMS320F28P650DK

Hi TI support team,

On the F28P65x eval board, I am trying to use an eCAP module to generate an interrupt when an external input signal has a positive pulse width greater than 100000 clock cycles. I used a function generator to inject a constant square wave on GPIO16. I saw that the eCAP module generated an interrupt, with the interrupt flag set to 1026 (0x402), after the code started. However, the interrupt fired only once with the constant-pulsed input. Is anything required to clear MUNIT_1_ERROR_EVT2 besides the interrupt flag? The following are my SysConfig settings for eCAP and the ISR code snippet.

Thanks,

Haobo

RE: TMS320F28P650DK: ECAP Signal Monitoring

Divesh Dang 18431815 — Fri, 08 May 2026 04:57:32 GMT

Hi,

Please try using Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP4) instead of the one used by you. Please note that group number for ECAPx module is 4.

Thanks,

Divesh

TMS320F28P650SK: S25FL128L SPI NVM not responding — SCLK/MOSI/CS active but no data on MISO

Antony Jose — Thu, 07 May 2026 10:09:01 GMT

Part Number: TMS320F28P650SK

I am interfacing an S25FL128L SPI flash with a TI F28P650SK6PZPR device using SPIA in non-FIFO polling mode.

Current observations:

SCLK is toggling correctly
MOSI is transmitting data correctly
CS is toggling correctly
No response is observed on the flash SO/MISO pin
SPIRXBUF always reads 0x0000
SPISTS.INT_FLAG becomes set (0x0040) after transmission and clears after reading RX buffer
SPI mode configured as Mode 0
RESET# and WP# pins are held HIGH

I tested JEDEC ID command (0x9F) using:

GPIO_writePin(GPIO_PIN_SPIA_PTE, 0);

SPI_transmitByte(SPIA_BASE, 0x9F);

id1 = SPI_transmitByte(SPIA_BASE, 0x00);
id2 = SPI_transmitByte(SPIA_BASE, 0x00);
id3 = SPI_transmitByte(SPIA_BASE, 0x00);

GPIO_writePin(GPIO_PIN_SPIA_PTE, 1);

SPI transfer function:

SPI_pollingNonFIFOTransaction(base, 8U, txData);

Additional observations:

SCLK and MOSI waveforms are visible on scope
No waveform observed on flash SO pin
CS timing appears correct
SPI baud rate currently 10 MHz
SPIDAT and SPIRXBUF remain 0.

Additionally, before testing the JEDEC ID (0x9F) command directly, I was using the following SPI exchange function for flash communication, but no valid data was being received.

SPI2_Status_TypeDef SPI2_Exchange1(uint8_t *pTransmitData,
                                   uint8_t *pReceiveData,
                                   uint16_t timeout)
{
    uint32_t tick = 0;
    uint16_t txData = (uint16_t)(*pTransmitData) << 8;
    uint16_t rxData = 0;
    uint16_t time_out = 0;

    uint32_t base = SPIA_BASE;

    while ((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) != 0) {
        if (++time_out >= SPI_TIMEOUT_COUNT) {
            return SPI2_ERROR;
        }
    }

    SPI_writeDataNonBlocking(mySPI0_BASE, txData);

    tick = 0;

    time_out = 0;
    while ((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) == 0) {
        if (++time_out >= SPI_TIMEOUT_COUNT) {
            return SPI2_ERROR;
        }
    }

    rxData = SPI_readDataNonBlocking(mySPI0_BASE);

    *pReceiveData = (uint8_t)(rxData & 0xFF);

    return SPI2_OK;
}

Since no valid response was received using this function, I simplified the test and directly tried reading the JEDEC ID using command 0x9F, but still no response was observed on the MISO/SO line.

What could cause the flash device to not drive the MISO/SO line even though clock, MOSI, and CS are active?

RE: TMS320F28P650SK: S25FL128L SPI NVM not responding — SCLK/MOSI/CS active but no data on MISO

Antony Jose — Fri, 08 May 2026 04:56:23 GMT

HI Aishwarya,

RE: TMS320F28P650DK: ECAP Signal Monitoring

Divesh Dang 18431815 — Fri, 08 May 2026 04:40:02 GMT

Hi Zhang,

Since interrupt is only generated once , there is something wrong in the interrupt configuration. At the end of the ISR, one needs to acknowledge the group interrupts for more interrupts to propagate. This is done by using function Interrupt_ClearACKGroup() in your code. I am not sure that your code is picking up correct group number (corresponding to the ECAP module you are using). Kindly check group number from table 3-2 given on page 144 of Technical Reference Manual. Here, group number is represented by row.

Based on the group number, you can choose enumerator ( INTERRUPT_ACK_GROUPx where x=group number corresponding to ecap module being used).

Also, there is no example other than named as "ecap_ex5_signal_monitor" which will emulate your test scenario.

Thanks,

Divesh

TMS320F28P650DH: Questions to Dual Core Program

Shengyue Zhong — Fri, 08 May 2026 03:42:21 GMT

Part Number: TMS320F28P650DH

Hi Team,

One of my customers is using F28P65, there are some confusion want to clarify, could you take a look and explain? Thanks a lot.

When program dual core

In CCS, before programming CPU2’s flash, must we always execute Configure Clock in the On‑Chip Flash Plugin for CPU1 firstly?
For the dual‑core F28P65 device, is there an officially recommended, streamlined flash‑programming flow?
When moving to mass production, can the programming steps for CPU1 and CPU2 be automated (e.g., with scripts or a command‑line tool) so we don’t have to manually configure the bank map and perform step‑by‑step flashing each time?

Regarding dual‑core firmware communication and upgrade, I’d like to confirm the recommended implementation approach:

When upgrading CPU2’s firmware, must CPU2 stay in reset or stopped state, or running?
Is it recommended that CPU1 write directly to the flash bank assigned to CPU2, then hand over those banks to CPU2 and ask CPU1 to start CPU2 afterwards?
During the upgrade, are there official guidelines on where Flash API calls should execute, RAM‑usage restrictions, and the appropriate timing for switching bank ownership?
Are there any official examples or reference documents for dual‑core upgrades on the F28P65?

We have also observed that dual‑core flashing is highly sensitive to the flash‑bank map and erase ranges. I would like to confirm the following:

Must the flash‑bank ownership for CPU1 and CPU2 exactly match the linker/map files of their respective projects?
When flashing CPU2, should we always use the “Necessary Sectors Only (for Program Load)” erase mode instead of a broader erase range?
For dual‑core F28P65 projects, is there an officially recommended flash‑bank allocation example?

TMS320F28P650DK: Error during import and compilation of the f28p65x_cpu1_echoback_solution routine

hao wang — Wed, 06 May 2026 07:38:02 GMT

Part Number: TMS320F28P650DK

HI,

SDK:C2000Ware_26_00_00_00

IDE: Version: 12.8.1.00005

I encountered an error when compiling the demo "f28p65x_cpu1_echoback_solution". The error message indicated that the file "ecat_def.ha" could not be found. For detailed error information, please refer to the attached image.

Please tell me how to deal with this problem. Thank you and looking forward to your reply.

RE: TMS320F28P650DK: Error during import and compilation of the f28p65x_cpu1_echoback_solution routine

hao wang — Fri, 08 May 2026 02:15:01 GMT

Thank you for your reply.This is helpful to me.

RE: TMS320F28P550SG: Debug probe cannot be invoked properly by CCS

Joe Ji — Fri, 08 May 2026 01:30:51 GMT

Hi Matt

it is the new design project. The ccs version is 20.5.

Thanks

Joe

TMS320F28P550SG: Debug probe cannot be invoked properly by CCS

Joe Ji — Thu, 07 May 2026 15:35:11 GMT

Part Number: TMS320F28P550SG

Hi Expert

Customer reports an issue that with the correct ccxml, the CCS cannot invoke the XDS110 debug probe properly, the XDS110 debug probe can be correct recognized by PC and CCS start page, pictures are below, do you have any suggestions on this issue?

besides the pictures below, I also checked:

Windows device management can recoginize XDS110
XDSDFU can properly involked and update XDS110 FW
CCXML file configuration works well in other computers

Thanks

Joe

RE: CODECOMPOSER: How to run code with code sections in flash and ram CCS v3.3 TMS320F28335

MatthewPate — Thu, 07 May 2026 23:42:28 GMT

As long as you set up the XINTF timing beforehand, you should be able to load the external RAM directly from CCS. Once that is configured the device should be read/write to the memory as if it were internal to the device. I think there may be a script if you have the 28335.ccxml defined as the target, under the Tools section in CCS.

If you are trying to do separate flash and RAM loads, that should work as well, so long as the XINTF is setup to interface with the external RAM correctly.

Later on, when you are preparing the final application you can use load/run option in the .cmd file to tell the linker that you will load the code to flash, but it will run from the external RAM. the only thing you will need to do in that case is perform a memory copy from flash to RAM before calling into those functions.

Best,

Matthew

CODECOMPOSER: How to run code with code sections in flash and ram CCS v3.3 TMS320F28335

Torgeir Jakobsen — Wed, 06 May 2026 16:17:46 GMT

Part Number: CODECOMPOSER

I am trying to run a project where I have a code section in internal FLASH and another code section in external RAM Zone6. I am using Code Composer Studio v3.3 and DSP/BIOS and the processor is the TMS320F28335.

I have congifured RAM Zone6 memory to have a range for code and have made a section which I have specified in the cmd-file to be located there.

I can see from the generated map-file that it places code in the Flash and in the external RAM Zone 6.

How do I get the RAM code loaded into external RAM before I start the debugging? Does it try to do it after the flashing? Or do I flash first and load the other code into flash afterwars? Do I have to make commands in the gel-file to load the RAM code section and how?

Later I will generate two hex-files, one for Flash and one for RAM. The Flash code will have code for reading the RAM hex-file into external RAM. The reason why I do this is because I am running out of FLASH memory space.

AM13E23019: How to understand the SPI Interrupt -- FIFO is at least 1/16 full - "not empty"

Joe Ji — Wed, 06 May 2026 11:54:52 GMT

Part Number: AM13E23019

Hi Expert

Customer uses SPI for SoC and MCU communication, when the SPI Interrupt is triggerd, the ISR read out all the data in SPI FIFO and ack. when customer using FIFO is ½ full interrupt, the interrupt can be triggerd and ISR run properly, but when customer using FIFO is at least 1/16 full - "not empty", the interrupt trigger Freq is less than expectation and data cannot be properly read out by ISR. I would like to understand how "not empty" triggered with this SPI design and how to use it properly?

Thanks and best regards

Joe

RE: AM13E23019: How to understand the SPI Interrupt -- FIFO is at least 1/16 full - "not empty"

Delaney Woodward — Thu, 07 May 2026 22:06:49 GMT

Hi Joe,

I see, yes that’s the behavior I would expect as well. Let me test this on my end and get back to you next week.

Best Regards,

Delaney

RE: F29H859TU-Q1: start CPU1 and CPU2 in one project

AJ Favela — Thu, 07 May 2026 21:26:56 GMT

Hi Jenny,

A multi-core project will always be necessary when using CPU2/3. The recommend and most reliable way to do this is to import an existing dual-core example from our SDK (such as empty_project_multi) as a template and implement the customer project to the CPU2 or CPU3 project files.

As you mentioned a CPU1 project is still needed to boot and release CPU2/CPU3 out of reset but it is also needed to give ownership of peripherals to CPU2/3. If you are using syscfg this is added to your board.c file once you have added a peripheral to the CPU2/3 section of the .syscfg file, just be sure to call board_init() within your CPU1 code. If you are not using syscfg, then you will need to manually call SysCtl_selectCPUForPeripheral(); and SysCtl_selectFrameForPeripheral(); within the CPU1 code to assign ownership before any configurations can happen. Configurations themselves need to happen within the assigned CPU that now has ownership or if using syscfg, can happen within that CPU's portion of the file.

Kind regards,
AJ Favela

F29H859TU-Q1: start CPU1 and CPU2 in one project

Jenney Ni — Thu, 30 Apr 2026 07:22:22 GMT

Part Number: F29H859TU-Q1

Hi all,

I saw we have many multi-core examples in the SDK. But they have one project for CPU1 and one project for CPU2. Can we combine these two project to one project.

Because customer have completely the whole function in CPU1's project. Now they want to split into cpu1 and cpu2. Is there aby easy way?

Regards,

Jenney

RE: TMS320F28P550SG: Debug probe cannot be invoked properly by CCS

Matt Kukucka — Thu, 07 May 2026 20:52:07 GMT

Hello,

[quote userid="521036" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1643589/tms320f28p550sg-debug-probe-cannot-be-invoked-properly-by-ccs"]CCXML file configuration works well in other computers[/quote]

Which CCS version is this on? Are the other computes using the same?

Best,
Matt

RE: TMS320F28P650SK: S25FL128L SPI NVM not responding — SCLK/MOSI/CS active but no data on MISO

Aishwarya Rajesh — Thu, 07 May 2026 20:34:55 GMT

Hi Antony,

Is the HOLD# pin on the external flash tied to VCC via a 10k pull up.

Ensure the SPI pins are configured for SPI originally?

You mentioned SCLK and MOSI is seen on the scope, is it correct? Keep in mind, the C2000 SPI peripheral sends MSB-first from bits [15:8] for 8-bit character length.

Best Regards,

Aishwarya

CCSTUDIO-THEIA: CCSTUDIO-THEIA settings bug: Compiler and SysConfig discovery is broken

Flemming Steffensen — Wed, 29 Apr 2026 13:11:18 GMT

Part Number: CCSTUDIO-THEIA

The Compiler and SysConfig discovery in CCS Settings is broken.

It's working as expected for C2000Ware.

This is tested on Windows 11. It's unknown if a similar issue exist on Linux and Mac.

Some background:

When installing several versions of CCS and C2000Ware from the release packages, the install folder gets to look like this:

With my setup, the expectation is that it's still possible to execute the four versions of CCS, and thereby be able to have the same features as when they were released - including use the LTS compiler and SysConfig that they came bundled with.

The problem.

The reality is that only the latest version of the Compiler and SysConfig is available for all of the installed CCS versions.

Going to File -> Preferences -> Code Compose Studio Settings.. in any of the installed CCS versions will unfortunately show exactly the same, as illustrated below.

Compilers:

As can be seen, the Compiler discovery-path defaults to the latest installed version, and secondary to the c:\ti folder - but it discovers nothing more that the latest version. Adding for example c:/ti/ccs2041 (or a version with slashes the other direction) does nothing to discover the earlier compilers. And editing the c:/ti/ccs2041 path or changing the search order is not possible.

Products:

It's slightly better on this pane.

The C2000Ware versions are correctly discovered, and thereby available to use by the projects.

However, the SysConfig is suffering from the same issues as the Compiler, that only only the latest version is available.

Expected:

If possible, please provide a quick workaround that allows selecting the old versions, and later provide a long-term fix.

Thanks.

RE: CCSTUDIO-THEIA: CCSTUDIO-THEIA settings bug: Compiler and SysConfig discovery is broken

Ki — Thu, 07 May 2026 19:57:47 GMT

[quote userid="671615" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1641522/ccstudio-theia-ccstudio-theia-settings-bug-compiler-and-sysconfig-discovery-is-broken/6336284"] IMHO CCS should have a default path entry that was similar to C:\ti\ccs???\ccs\tools\compiler and C:\ti\ccs????\ccs\utils for products.[/quote]

This would work for environments where CCS is installed in the default locations. I suppose it is worth a look to at least support those cases.

TMS320F280049C: BISS-C lib and test for TMS320F280049C

Frank Fang — Mon, 04 May 2026 15:03:14 GMT

Part Number: TMS320F280049C

We are trying to support BISS-C encoder on LAUNCHXL-28F0049C. However, the C2000Ware_MotorControl_SDK_5_04_00_00 only include library and example CCS project for F28P65x device, they are mentioned in the following TI BISS-C documents. Can you provide .lib and example CCS project for LAUNCHXL-28F0049C? or some instructions how to change device specific files or library from F28P65x to LAUNCHXL-28F0049C support?

BiSS-C Absolute Encoder, Master-Interface Reference Design for C2000™ MCUs (Rev. B)

C2000 BiSS-C Encoder Interface Software Guide (pdf)

RE: TMS320F280049C: BISS-C lib and test for TMS320F280049C

Frank Fang — Thu, 07 May 2026 19:36:15 GMT

Hi Peter,

Thank you for your information.

RE: TMS320C28346: Pin assignment for C28 Dual-core chip

AJ Favela — Thu, 07 May 2026 19:17:51 GMT

Jwalant,

Let me redirect this question to an SCI expert, as the interrupt issue looks to be more at the peripheral level rather then a multi-core level. Please give them some time to respond.

Kind regards,
AJ Favela