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Cannot single step supervisor instructions

Ulf Samuelsson
Expert 1010 points
Other Parts Discussed in Thread: TMS570LC4357, HALCOGEN

Trying to help a colleague with a "bricked" TMS570LC4357 CPU Module.

It is not possible to flash the part since the flashloader fails.

My colleague has used CCS and I am trying IAR EWARM 8.50.10 FS.

The board has the JTAG reset connected to the cold reset (W7 = nPORRST) which is probably a mistake
since the reset is not proper. The CPU runs and then is stopped by the debugger which resets the PC to 0.

I have tried flashing with XDS200, I-Jet and a J-Link. All fails.

We suspect that the faulty program makes it impossible to execute code, maybe screwing with the MPU.

If I use a J-Link and connect to a running system, I can reset, but single step stops before executing the instruction

I have managed to rewire the J-Link and connect the JTAG reset to Warm Reset (B17= nRST).
When I do this, I can attach to the running system, apply a reset.
The CPU is now running in Supervisor Mode (M=0b10011).
The program stops at the beginning of the faulty application.

I then download an application to RAM and.
set the PC to the beginning of the application.
Single step works until I get to an instruction which is privileged. I.E: MRS.
Then the PC is frozen at that point.

I can change the Program Counter past the privileged instruction and can single step
until I encounter another privileged instruction.

If I use a working board, it will also set M=0b10011, and then single stepping is fine.

Is there anything else that is needed to single step privileged instructions?

  • 0
    TI__Guru**** 186206 points

    In privileged processor mode the software can use all the instructions and has access to all resources. The the CPSR can not be written in user mode. 

    When nRESET is driven from LOW to HIGH, the CPU forces CPSR M[4:0] to b10011 (Supervisor mode). The code may enter system mode or user mode after configurating the MCU general registers and configuring the exception modes.

  • 0
    Expert 1010 points

    The debugger reports the CPSR.M as b10011.

    The only thing that gets single stepped is a BL (branch and link) to a subroutine  (this is generated by HALCoGen)

    that starts clearing the registers which works until the first MSR/MRS instruction.

    Is there any external signal that could block?

    Any possible trap?

    The probe is set up to trap on aborts, reset etc...

  • 0 in reply to Ulf Samuelsson
    TI__Guru**** 186206 points

    Hi Ulf,

    Did you figure out what causes the problem? 

  • 0 in reply to QJ Wang
    Expert 1010 points

    No, the CPU is running properly if I powercycle the board but is not possible to reflash.
    With the JTAG reset connected to nPORRST it is not possible to single step.
    With the JTAG reset connected to nRESET I can single step ordinary instructions but not MRS.
    I can connect the J-Link this way by using a 20-pin "spider cable" instead of a flat-cable
    so I can easily reroute to nRESET which is on a header.

    The J-Link has some issues with EWARM, and I plan to try with an I-Jet but need an adapter from
    the I-Jet MIPI-20 to an ARM -20 connector (2x20 2,54mm spacing) so I can use the spider cable.
    I will try to find such an adapter for the XDS200 as well.

    I have looked at the PSR when connecting to a working unit, and it has the same value for the M field.

    The probes have a capability to break on exceptions, and I thought maybe an exception is triggered
    so I cleared the checkmarks for all exceptions, but no luck.

    When I connect the I-Jet with the JTAG connected to the nPORRST the debugger mentions an external event. The debugger should not assert the nPORRST and there is nothing driving the nRESET.
    Are there other reasons why the CPU may fail to execute instructions?

    Since the single step with the JTAG=nRESET works until a privileged instruction is executed
    an external signal seems to be an unlikely cause.

    The CPU might be broken of course.

  • 0 in reply to Ulf Samuelsson
    TI__Guru**** 186206 points

    The MSR is used to move data from MCU general registers to CPSR, and MRS is used to read CPSR register. The CPSR can not be written in user mode, but the CPSR can be read in user mode. Writing to CPSR in user mode has no effect, and CPU should not hang at this instruction.

    In user mode, accessing P15 with MRC/MCR instructions will generate UNDEF abort, but the CPU should not hang at MRC/MCR instruction.

    So I am not very sure if the CPU is broken or not.