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Original question:

TMS570LC4357: ESM 1.26 Error by writing to ECC SRAM of Level 2 SRAM?

TMS570LC4357: Error generate during RAM12 and RAM17 Diagnostics

Max Wittekind
Expert 1755 points
Part Number: TMS570LC4357

Hi experts,

I am a little confused by the description of the RAM12 and RAM17 in the Technical Reference Manual section 8.2.6 compared to the implementation in the diagnostic library.

Step 4 in the Manual states: "No error bit will be set if no error is detected in the diagnostic test. The diagnostic errors will also be sent to ESM group 2 as "uncorrectable error type B"
Because of this I thought, that setting of any error Bit or the ESM would indicate that the Address decode and ECC are malefunctioning. However when I checked the Safe TI Library I noticed, that after the Test has passed the RAMERRSTATUS bits get cleared as well as the nERROR.

(Q1) Can you tell me which Bits get set when the test passes?

(Q2) Is ESM 2.7 set even when the test passes?

Thank you and best regards,
Max

  • +1
    TI__Guru**** 186246 points

    Hello MAx,

    If you force a ECC error (DIAG_ECC), the test pass means the ESM2.7 and bit 19/21 of RAM ERR Status are set. If ECC value (DIAG_ECC) of test vector is correct, the equality/in-equality test pass means there is no error flag in RAM ERR status register and ESM registers.