RTI in TMS470MF066 HDK

The UC Compare (up counter compare) is the divider that is applied to the RTICLK to generate the counter output clock frequency. By default, the RTICLK is 80MHz. If you select a 10MHz counter frequency, HALCoGen calculates an UC Compare of 7 (divide by 7+1). The update compare values (0-3) are the values compared to the counters to generate the interrupts. For example, with a 10MHz counter frequency if you set the compare 0 period to 1ms, HALCoGen sets both the Update Compare 0 and the Compare 0 values to 1000. When the selected counter reaches 1000, the counter is reset and the update compare 0 value is loaded into the compare 0 register. The use of two registers means that the update to the compare register only happens when the counter is reset. This is done to avoid missing a compare when updating the compare register. The "Counter Freq", what you request in MHz, and the "Counter Output Clock Frequency" , what you actually get, may be different if the frequency you requested is not an integer division of the RTICLK frequency.