Other Parts Discussed in Thread: HALCOGEN
I have been studying the calibration and offset error correction sequences by reviewing section 16 of the SPNU0603A technical reference manual for the TMS570LS0232, and the available documentation has raised quite a few questions:
(1) Where do I find the formula for the calculated 2s complement error correction value to load into the ADCALR register (per section 16.7.1.2)?
(2) From what I can tell, this is only an offset calibration value, and there is no practical way to calculate and compensate for gain error. Is this correct?
(3) Section 16.7.1 describes 'conversion of an embedded calibration reference voltage', but figures 16-11 and 16-13 indicate that the reference voltage used is ADREFHI / ADREFLO. This is a shared pin on the TMS570LS0232 with VCCAD and VSSAD. Does this mean that this IC does not have an internal reference, and hence calibration capability is limited?
(4) Am I correct is saying that even with offset error calibration, we're only really improving the offset error from +/-4LSB to +/-2LSB across the full operating temperature range in 12 bit mode?
(5) Am I also correct in stating that the differential non-linearity error is only improved from +/-7 LSBs to +/-4LSBs across the full operating temperature range in 12 bit mode when offset error calibration is employed.
(6) Once you have computed the midpoint value, D(cal), as shown in figure 16-12 of the TMS570LS0232 technical reference manual, how are you supposed to use that number? Is it indicative of a linearity error term (i.e. curved instead of straight) or a slope error term (i,e, error will be twice as far from ideal at maximum input voltage).
(7) If the offset error is negative, do you need to calibrate only using reference values > 0. In other words, don't use VRefLo on its own (Bridge_en=1, HILO=0) if it is connected to Vss, since the actual offset could be as low as -4. This will return an ADC result of 0 resulting in an erroneous offset calculation?
Thanks
Jeff Cranmer