I've been studying the section on Primary SRAM Hard Error Cache and Livelock (diagnostic RAM2).
The documentation states:
"Since ECC correction is enabled, corrected data values will be stored in an internal one entry hard error cache, rewritten to the SRAM, and re-fetched from the SRAM.
A single instruction and its data may not have more than one correctable error. In case more than one correctable error is detected, it is possible to overrun the hard error cache and put the processor into an inoperable livelock state. Cases that can generate a livelock include:
• Two single bit errors in a 64-bit unaligned 32-bit Thumb-2 instruction fetch
• A single bit error in a load instruction (LDR or LDM) followed by a single bit error in the instruction's data payload
I'm having difficulty determining exactly what it means by having the processor put into an inoperable 'livelock' state. Does this mean that all processing operations cease? Are these the errors that cause error source 'TCM - ECC livelock detect' (group 2, channel 16), or are they the errors which cause a RAM bank ECC uncorrectable error (Group 3, channel 3 and group 3, channel 5)?
If the latter, then is the effect of an abort (CPU) just to stop processing and wait for a watchdog reset?
