Hello,
The SL_SelfTest_SRAM tests do not leave the controller in the same state as before the tests are run.
The some odd & even RAM error status bits are left set.
The odd & even ECC memory writes are left on.
The odd & even ECC threasholds are changed.
The odd & even test modes are left on.
There is nothing in the SafeTIDiagnosticLibrary-User'sGuide-v2.3.1 that explains that there are post-test steps required.
Am I missing an errata?
Regards,
Mark.